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Dft Manager Jobs (NOW HIRING)

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$147K - $272K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$147K - $272K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$126K - $190K/yr

... manage multiple priorities Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 0 Years of Experience Pay & Benefits At Apple, base pay is ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

Apple

SoC DFT DV Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience.

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$126K - $190K/yr

... manage multiple priorities Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 0 Years of Experience Pay & Benefits At Apple, base pay is ...

Draper

Design for Test (DFT) Engineer

Cambridge, MA · On-site

$95K - $245K/yr

We are seeking an experienced DFT Engineer to join our team. The successful candidate will be ... Ability to manage small technical teams * Excellent verbal and written communication skills

Eridu AI

DFT Lead

Saratoga, CA · On-site

$210K - $275K/yr

Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

Apple

SoC DFT DV Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience.

Apple

SoC DFT DV Engineer

Austin, TX · On-site

$181K - $318K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience.

Draper

Design for Test (DFT) Engineer

Cambridge, MA · On-site

$95K - $245K/yr

We are seeking an experienced DFT Engineer to join our team. The successful candidate will be ... Ability to manage small technical teams * Excellent verbal and written communication skills

Draper Labs

Design for Test (DFT) Engineer

Cambridge, MA · On-site

$95K - $245K/yr

We are seeking an experienced DFT Engineer to join our team. The successful candidate will be ... Ability to manage small technical teams * Excellent verbal and written communication skills

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Dft Manager information

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$28.5K

$62.7K

$113.5K

How much do dft manager jobs pay per year?

As of Jun 5, 2026, the average yearly pay for dft manager in the United States is $62,661.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,000.00 and $69,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT (Design for Test) Manager, and why are they important?

To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.

What are some common challenges a DFT Manager faces when coordinating between design and test teams?

A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.

What are DFT Managers?

DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.

What is the difference between Dft Manager vs Dft Engineer?

AspectDft ManagerDft Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniquesBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools
Work EnvironmentOversees DFT teams, manages testing strategies, collaborates with design and manufacturingPerforms DFT design, implements test structures, analyzes test data
Industry UsageUsed in semiconductor and integrated circuit industries for testability managementUsed in semiconductor design for implementing testability features

The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.

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Dft Manager jobs near you
Infographic showing various Dft Manager job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 83% Full Time, 15% Part Time, and 1% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $62,661 per year, or $30.1 per hour.

Silicon Design-for-Test (DFT) Engineer

MatX

Mountain View, CA • On-site

$175K - $450K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 3 days ago

Job description

What MatX Is Building
MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking a Silicon Design-For-Test (DFT) engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity and other key technologies in leading-edge process nodes.
What You'll Do Here
  • Design and develop functional test solutions for SERDES PHY, covering loopback, eye diagram characterization, and margin testing.
  • Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.
  • Develop and maintain firmware loading flows for PHY bring-up and test - including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development.
  • Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE.
  • Execute DFT implementation and verification flows for block-level DFT insertion, including scan chain closure, ATPG pattern generation, and sign-off.
  • Support test escapes root cause analysis and drive continuous improvement of DFT coverage and test quality.

Who You Are
  • Hands-on experience with DFT implementation - MBIST, at-speed scan and scan compression.
  • Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
  • Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.
  • Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.
  • Experience with system-level DFT access - hierarchical test access, test data compression, and multi-die/chiplet DFT - is a strong plus.
  • Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent.

Compensation
The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.
  • Early Career - $120,000 - $275,000 + equity
  • Mid Career - $175,000 - $450,000 + equity
  • Senior Career - $275,000 - $600,000 + equity

What We Offer
  • A Stake in our success A flexible cash equity compensation mix that fits your needs
  • Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don't)
  • Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
  • Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
  • Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
  • Team Connection Team Lunches, quarterly off-sites, and regular town halls
  • Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don't!
  • Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
  • Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
  • MatX E[x]tras $50 per month to use on the perks you care about most
  • Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.
All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.
This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.
MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

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