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Dft Manager Jobs (NOW HIRING)

SoC DFT DV Engineer

Austin, TX · On-site

$122K - $161K/yr

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...

... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...

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Dft Manager information

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$28.5K

$62.7K

$113.5K

How much do dft manager jobs pay per year?

As of Jul 19, 2026, the average yearly pay for dft manager in the United States is $62,661.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,000.00 and $69,000.00 per year, depending on experience, location, and employer.

What are DFT Managers?

DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.

What is the difference between Dft Manager vs Dft Engineer?

AspectDft ManagerDft Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniquesBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools
Work EnvironmentOversees DFT teams, manages testing strategies, collaborates with design and manufacturingPerforms DFT design, implements test structures, analyzes test data
Industry UsageUsed in semiconductor and integrated circuit industries for testability managementUsed in semiconductor design for implementing testability features

The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.

What are some common challenges a DFT Manager faces when coordinating between design and test teams?

A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.

What are the key skills and qualifications needed to thrive as a DFT (Design for Test) Manager, and why are they important?

To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.
More about Dft Manager jobs
What cities are hiring for Dft Manager jobs? Cities with the most Dft Manager job openings:
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What states have the most Dft Manager jobs? States with the most job openings for Dft Manager jobs include:
Infographic showing various Dft Manager job openings in the United States as of July 2026, with employment types broken down into 1% Locum Tenens, 77% As Needed, 20% Full Time, and 2% Summer. Highlights an 93% Physical, 5% Hybrid, and 2% Remote job distribution, with an average salary of $62,661 per year, or $30.1 per hour.
Semicustom DFT Strategy Lead

Semicustom DFT Strategy Lead

Advanced Micro Devices, Inc

Austin, TX • On-site

$205K/yr

Full-time

Re-posted 22 days ago


Advanced Micro Devices rating

8.4

Company rating: 8.4 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

26th of 143 rated electronics manufacturers


Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
About the department
Central DFX (CDFX) is a centralized ASIC design group within AMD's Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console, and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.
THE PERSON:
You are a senior leader with extensive knowledge and experience across the areas of DFT and testing. You thrive in an environment that is 'Lead by influence' where success is measured by achieving the optimal tradeoff of an often-conflicting set of goals: schedule, Power/Performance/Area, cost and especially quality ( DPPM ). You are looking to nurture deep relationships with Design and Product teams to gather best practices, understand needs, guide the use of tools and flows, and listen to feedback for process improvement. Lastly, you are looking for an opportunity where you can synthesize this input and make a demonstrable impact on a World-Class test strategy; on the innovation of advanced test techniques; on setting industry direction through standards and engagement with the Industry test community; and keeping AMD"s Test Professionals informed and engaged with the creation and execution of a vigorous DFT Roadmap.
KEY RESPONSIBILITIES:
  • Work closely with SOC and PDG teams to drive adoption of and ensure compliance with the company-wide DFT strategy that is continuously aligned with the strategies for the Design, Product Engineering, and Quality functions.
  • Continually and successfully advocate for maintaining testability features while designs work through various stages, ie floor planning, timing closure, etc.
  • Follow up with post-silicon experiments to analyze the effectiveness of DFT features to determine their return on investment to justify ongoing usage.
  • Influence and drive outside partners in the EDA and ATE industries.
  • Evaluate outside available tools and make decisions on Build vs Buy.
  • When Build decisions are made, be able to lead and manage a team to architect and implement the internal solution, then see it through to deployment and maintenance.

PREFERRED EXPERIENCE:
  • Extensive and Senior knowledge in DFT and Testing for semiconductor designs.
  • Proven ability and experience with defining a world-class DFT roadmap strategy.
  • Proven ability to drive enterprise and cross-department collaboration for DFT across a design organization.
  • Proven ability and experience partnering with industry leading EDA and ATE companies.
  • Knowledge with current and industry leading EDA and ATE tools.
  • Experience developing and deploying internal DFT Tools successfully.

ACADEMIC CREDENTIALS:
  • Bachelor's or Master's degree in electrical engineering, Computer Engineering, or a related field preferred.

LOCATION: Austin, Tx.
#LI-MR1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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