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Dft Manager Jobs (NOW HIRING)

GlobalFoundries

DFT architect / lead

Austin, TX · On-site

$153K - $265K/yr

This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs-spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management.

Globalfoundries

DFT architect / lead

Richardson, TX

$153K - $265K/yr

This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs-spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management.

Globalfoundries

DFT architect / lead

Richardson, TX

$153K - $265K/yr

This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs-spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management.

EnCharge AI

Principal DFT Engineer

$180K - $220K/yr

Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...

EnCharge AI

Principal DFT Engineer

OR · Remote

$180K - $220K/yr

Experience managing DFT in multi-voltage/power-gated designs-crucial for edge efficiency. The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be ...

GlobalFoundries

DFT architect / lead

Austin, TX · On-site

$153K - $265K/yr

This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs-spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management.

Broadcom, Inc.

DFT Engineer

San Jose, CA · On-site

$120K - $192K/yr

Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will ... Must be self-driven engineer with good project management and organizational skills to deliver high ...

Intel

Experienced DFT ATPG Engineer

Santa Clara, CA · On-site

$105K - $200K/yr

The DFT ATPG engineer develops the logic design, register transfer level (RTL) coding, simulation ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

Intel

$105K - $200K/yr

The DFT ATPG engineer develops the logic design, register transfer level (RTL) coding, simulation ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

Apple

SoC DFT DV Engineer

Austin, TX · On-site

... manage multiple prioritiesAbility to lead project executionGood knowledge of general logic design, and exposure to DFT is a plus

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How much do dft manager jobs pay per year?

As of Jun 5, 2026, the average yearly pay for dft manager in the United States is $62,661.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,000.00 and $69,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT (Design for Test) Manager, and why are they important?

To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.

What are some common challenges a DFT Manager faces when coordinating between design and test teams?

A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.

What are DFT Managers?

DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.

What is the difference between Dft Manager vs Dft Engineer?

AspectDft ManagerDft Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniquesBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools
Work EnvironmentOversees DFT teams, manages testing strategies, collaborates with design and manufacturingPerforms DFT design, implements test structures, analyzes test data
Industry UsageUsed in semiconductor and integrated circuit industries for testability managementUsed in semiconductor design for implementing testability features

The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.

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Dft Manager jobs near you
Infographic showing various Dft Manager job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 83% Full Time, 15% Part Time, and 1% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $62,661 per year, or $30.1 per hour.
DFT architect / lead

DFT architect / lead

GlobalFoundries

Austin, TX • On-site

$153K - $265K/yr

Full-time

Posted 16 days ago

GlobalFoundries rating

8.2

Company rating: 8.2 out of 10

Based on 34 frontline employees who took The Breakroom Quiz

78th of 515 rated manufacturers

Job description

The DFT architect / lead engineer serves as a technical authority and strategic lead in designing and deploying industry-leading Design-for-Test (DFT) architectures. This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs-spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management. You will drive innovation in test methodology to achieve world-class quality, minimize test cost, and ensure seamless transition from pre-silicon RTL to high-volume manufacturing (HVM).
Your Job
  • Architectural Leadership: Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet-based designs.
  • Test Strategy Optimization: Develop advanced strategies for defect-oriented testing and optimize pattern volumes to balance aggressive coverage targets with tester memory constraints and test time.
  • Cross-Functional Integration: Lead the integration of DFT requirements into RTL, Synthesis, and Physical Design (STA/PD) flows. Drive "Design for Manufacturability" (DFM) initiatives to improve yield.
  • Silicon Bring-up & Debug: Spearhead post-silicon validation and silicon bring-up. Own the root-cause analysis of complex test failures and provide expert-level debugging of ATE/System-level failures.
  • Methodology & Automation: Architect and maintain scalable, high-performance DFT flows using TCL, Python, or Perl. Evaluate and benchmark emerging EDA tool features to stay ahead of technology nodes (5nm/3nm and beyond).
  • Mentorship & Influence: Provide technical mentorship to junior and senior engineers. Act as a consultant for RTL/DV/PD/STA teams to proactively address timing or routing issues caused by DFT structures.
  • Technical Documentation: Author comprehensive DFT specifications and strategy documents that serve as the "Gold Standard" for current and future project iterations.
  • Device Execution: At times, will need to own device execution, lead a team through spec, integration, verification and into silicon bring-up.

Other Responsibilities
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications
  • Education: Bachelor's, Master's, in Electrical Engineering, Computer Engineering, or related fields.
  • Experience: 7+ years of hands-on DFT experience with a proven track record of successfully taping out multiple complex SoCs. Must have silicon debug experience including, 1st silicon bring-up, characterization, customer debug, and ramp to production.
  • Tool Mastery: Expert-level proficiency with industry-standard EDA suites (e.g., Synopsys TestMAX/DFTMAX, Cadence Modus, or Siemens/Mentor Tessent).
  • Advanced Logic Knowledge: Deep understanding of scan compression architectures, hierarchical DFT, and mixed-signal test integration.
  • Scripting: Advanced proficiency in TCL and Python/Perl for developing custom CAD attributes and automating complex EDA flows.
  • Problem Solving: Demonstrated ability to solve timing closure issues related to DFT or complex ATPG coverage gaps.

Preferred Qualifications
  • Specialized Flows: Experience with Automotive ASIL-D functional safety requirements, including In-System Test (IST) and periodic logic/memory monitoring.
  • Advanced Packaging: Knowledge of 2.5D/3D IC testing, TSV probing, or HBM test strategies.
  • Yield Analysis: Experience with Volume Diagnostics and Yield Learning tools to drive DPPM reduction.
  • Industry Presence: Active participation in technical conferences or a history of contributing to patented DFT innovations.

Expected Salary Range
$153,000.00 - $265,000.00
The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law

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