Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test * In-system ...
Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test * In-system ...
DFT Design Engineer
Boxborough, MA · On-site
$126K/yr
... Management to deliver successful and timely project outcomes. THE PERSON: As part of AMD ... Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
DFT Design Engineer
Boxborough, MA · On-site
$126K/yr
... Management to deliver successful and timely project outcomes. THE PERSON: As part of AMD ... Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
Semicustom DFT Strategy Lead
Austin, TX · Hybrid
When Build decisions are made, be able to lead and manage a team to architect and implement the ... Extensive and Senior knowledge in DFT and Testing for semiconductor designs. * Proven ability and ...
Semicustom DFT Strategy Lead
Austin, TX · Hybrid
When Build decisions are made, be able to lead and manage a team to architect and implement the ... Extensive and Senior knowledge in DFT and Testing for semiconductor designs. * Proven ability and ...
DFT Design Engineer
Boxborough, MA · Hybrid
... Management to deliver successful and timely project outcomes. THE PERSON: As part of AMD ... Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
DFT Design Engineer
Boxborough, MA · Hybrid
... Management to deliver successful and timely project outcomes. THE PERSON: As part of AMD ... Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc ... Manage Gate-Level Simulation (GLS) verification, tape-out (TO) signoff, pattern delivery, and post ...
Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc ... Manage Gate-Level Simulation (GLS) verification, tape-out (TO) signoff, pattern delivery, and post ...
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Silicon Design-for-Test (DFT) Engineer
Mountain View, CA · On-site
$175K - $450K/yr
The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management ...
Silicon Design-for-Test (DFT) Engineer
Mountain View, CA · On-site
$175K - $450K/yr
The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management ...
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Good knowledge of general logic design, and exposure to DFT is a plus
GPU DFT Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
... manage multiple priorities Good knowledge of general logic design, and exposure to DFT is a plus
Silicon Design-for-Test (DFT) Engineer
Mountain View, CA · On-site +1
$175K - $450K/yr
The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management ...
Silicon Design-for-Test (DFT) Engineer
Mountain View, CA · On-site +1
$175K - $450K/yr
The successful candidate for this role will be responsible for implementation of DFT functions for performant and functionally accurate silicon for MatX products across compute, memory management ...
SoC DFT DV Engineer
Austin, TX · On-site
$122K - $161K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
SoC DFT DV Engineer
Austin, TX · On-site
$122K - $161K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus
GPU DFT Design Verification Engineer
Austin, TX · On-site
$90 - $120/hr
Experience working under strict schedule deadlines with the ability to manage multiple priorities * Good knowledge of general logic design, and exposure to DFT is a plus Apple is an equal opportunity ...
GPU DFT Design Verification Engineer
Austin, TX · On-site
$90 - $120/hr
Experience working under strict schedule deadlines with the ability to manage multiple priorities * Good knowledge of general logic design, and exposure to DFT is a plus Apple is an equal opportunity ...
GPU DFT Design Verification Engineer
$184K - $324K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$184K - $324K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$184K - $324K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$184K - $324K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 10 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$150K - $277K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$150K - $277K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...
Sr. Design for Test (DFT) Engineer
Boston, MA · On-site
$154K - $218K/yr
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Sr. Design for Test (DFT) Engineer
Boston, MA · On-site
$154K - $218K/yr
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
GPU DFT Design Verification Engineer
$150K - $277K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...
GPU DFT Design Verification Engineer
$150K - $277K/yr
... manage multiple priorities Ability to lead project execution Good knowledge of general logic design, and exposure to DFT is a plus Minimum Qualifications Bachelors Degree + 3 Years of Experience Pay ...
Sr. Design for Test (DFT) Engineer
Mountain View, CA · On-site
$164K - $185K/yr
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Sr. Design for Test (DFT) Engineer
Mountain View, CA · On-site
$164K - $185K/yr
Validate DFT implementation and requirements ... Proactively solve problems while managing deliverables in a fast-paced, evolving environment.
Dft Manager information
See salary details
$28.5K - $36.2K
9% of jobs
$36.2K - $44K
15% of jobs
$44.3K is the 25th percentile. Wages below this are outliers.
$44K - $51.7K
16% of jobs
The median wage is $57.3K / yr.
$51.7K - $59.4K
14% of jobs
$66.5K is the 75th percentile. Wages above this are outliers.
$59.4K - $67.1K
23% of jobs
$67.1K - $74.9K
8% of jobs
$74.9K - $82.6K
3% of jobs
$82.6K - $90.3K
3% of jobs
$90.3K - $98K
4% of jobs
$98K - $105.8K
2% of jobs
$105.8K - $113.5K
2% of jobs
$28.5K
$62.7K
$113.5K
How much do dft manager jobs pay per year?
As of Aug 9, 2026, the average yearly pay for dft manager in the United States is $62,661.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,000.00 and $69,000.00 per year, depending on experience, location, and employer.
What is a DFT manager?
DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.
What is the difference between Dft Manager vs Dft Engineer?
| Aspect | Dft Manager | Dft Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniques | Bachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools |
| Work Environment | Oversees DFT teams, manages testing strategies, collaborates with design and manufacturing | Performs DFT design, implements test structures, analyzes test data |
| Industry Usage | Used in semiconductor and integrated circuit industries for testability management | Used in semiconductor design for implementing testability features |
The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.
What are some common challenges a DFT manager faces when coordinating between design and test teams?
A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.
What are the key skills and qualifications needed to thrive as a DFT manager?
To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.
More about Dft Manager jobs
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What states have the most Dft Manager jobs? States with the most job openings for Dft Manager jobs include:
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Re-posted yesterday
Job description
About Positron AI
Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
Role Overview
Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.
Key Responsibilities
Own the Positron DFT strategy
Hands-on DFT implementation
Drive pre-silicon DFT verification
Partner with Physical Design
Own external DFT execution
Cross-functional leadership
AI-enabled engineering
Required Qualifications
Preferred Qualifications
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
If you are excited about ensuring the highest quality AI hardware and leading an advanced team, we want to hear from you! Apply today.
Compensation and Benefits
The base salary range for this role is $200,000 - $350,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.
Benefits & Perks
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
Health and wellness
Time off and flexibility
Compensation and future
Visa Support
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.
Positron AI specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.
Role Overview
Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.
Key Responsibilities
Own the Positron DFT strategy
- Define and maintain the DFT architecture for Asimov and future ASIC generations.
- Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives.
- Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization.
Hands-on DFT implementation
- Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features.
- Integrate DFT into internally developed RTL.
- Evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
Drive pre-silicon DFT verification
- Develop comprehensive DFT verification plans.
- Validate DFT functionality through simulation and gate-level verification.
- Ensure structural coverage targets are achieved before tapeout.
- Drive DDA, stuck-at, transition, cell-aware, and power-aware ATPG strategies.
- Own DFT signoff.
Partner with Physical Design
- Work closely with backend implementation teams to ensure successful physical realization of DFT architecture.
- Guide scan chain partitioning, compression planning, and test clock architecture.
- Address power-aware test implementation, timing closure considerations, and test mode integration.
Own external DFT execution
- Serve as Positron's technical lead for all DFT work performed by external design services partners.
- Review implementation quality and conduct design reviews.
- Drive issue resolution.
- Define deliverables and acceptance criteria.
- Ensure external work meets Positron quality standards.
Cross-functional leadership
- Partner closely with RTL designers, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT is designed in from architecture through silicon bring-up.
AI-enabled engineering
- Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG analysis, coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
- Continuously evaluate new AI techniques that accelerate DFT development while improving quality.
Required Qualifications
- BS, MS, or PhD in Electrical Engineering or Computer Engineering
- 12+ years of ASIC development experience
- Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts
- Strong understanding of scan architectures, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, test compression, fault models, and structural coverage analysis
- Experience with leading DFT tool suites (e.g., Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or equivalent)
- Strong RTL skills using Verilog/SystemVerilog
- Experience with synthesis and gate-level verification
- Strong scripting skills (Python, Tcl, Perl, or similar)
- Excellent debugging skills across RTL, netlists, and silicon test
- Demonstrated ability to drive technical execution across cross-functional engineering teams
Preferred Qualifications
- Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures
- High-speed SerDes and advanced process nodes (5nm and below)
- Low-power design, yield enhancement methodologies, and manufacturing test optimization
- Silicon bring-up, failure analysis, and post-silicon debug
- Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test
- In-system debug and observability: experience architecting debug infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up
- Emulation and pre-silicon validation: familiarity with Palladium/ZeBu/Veloce or FPGA prototyping to validate DFT features before tapeout
- Third-party IP integration: experience auditing, integrating, and validating DFT collateral from multiple IP vendors to ensure a coherent full-chip DFT architecture, not just block-level stitching
Leveling & Scope
While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Why Join Us?
- Be part of a rapidly growing AI startup shaping the future of AI hardware
- Work on groundbreaking technology with a highly skilled and passionate team
- Competitive salary, equity, and comprehensive benefits package
- Flexible work environment with remote work options
If you are excited about ensuring the highest quality AI hardware and leading an advanced team, we want to hear from you! Apply today.
Compensation and Benefits
The base salary range for this role is $200,000 - $350,000.
Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.
At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.
Benefits & Perks
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.
Health and wellness
- Fully company-paid medical, dental, and vision insurance for you and your dependents
- Company-paid life and disability coverage, with voluntary options to add more
- Supplemental hospital, critical illness, and accident coverage available
Time off and flexibility
- Unlimited paid time off - we encourage everyone to truly unplug and recharge
- 13 paid company holidays
- Remote-first culture with a company-provided computer and home office setup
Compensation and future
- Competitive salary and equity
- 401(k) with company matching, eligible from day one
Visa Support
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.
Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.