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Dft Manager Jobs in Seattle, WA (NOW HIRING)

Fortive

Global NPI Test Engineer

Everett, WA · On-site

Drive Design for Testability (DFT) reviews with product development teams. Test Development ... Risk Management & Product Quality * Participate in DFMEA and PFMEA activities to identify product ...

Fortive

Global NPI Test Engineer

Everett, WA · On-site

Drive Design for Testability (DFT) reviews with product development teams. Test Development ... Risk Management & Product Quality * Participate in DFMEA and PFMEA activities to identify product ...

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA · On-site

$170K - $250K/yr

... DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...

Kapta Space

Senior PCB Designer

Redmond, WA · On-site

Serve as point of contact for standardized PCB layout , DFM/DFA/DFT rules, ECAD constraint management, and centralized component-library oversight . * Partake in formal design reviews, enforce design ...

Kapta Space

Senior PCB Designer

Redmond, WA · On-site

$110K - $145K/yr

Serve as point of contact for standardized PCB layout , DFM/DFA/DFT rules, ECAD constraint management, and centralized component-library oversight . * Partake in formal design reviews, enforce design ...

New

Kapta Space

Senior PCB Designer

Seattle, WA · On-site

Serve as point of contact for standardized PCB layout , DFM/DFA/DFT rules, ECAD constraint management, and centralized component-library oversight . * Partake in formal design reviews, enforce design ...

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All JobsDft JobsDft Manager JobsDft Manager Jobs in Seattle, WA

Dft Manager information

See Seattle, WA salary details

$32.4K

$71.3K

$129.2K

How much do dft manager jobs pay per year?

As of Aug 22, 2026, the average yearly pay for dft manager in Seattle, WA is $71,310.00, according to ZipRecruiter salary data. Most workers in this role earn between $51,200.00 and $78,500.00 per year, depending on experience, location, and employer.

What is a DFT manager?

DFT Managers are professionals who oversee the Design for Testability (DFT) strategy and implementation within semiconductor design projects. They are responsible for leading teams that develop and integrate test features into integrated circuits (ICs) to ensure efficient manufacturing testing and product quality. DFT Managers coordinate with design, verification, and test engineering teams to optimize test coverage, reduce test costs, and ensure that chips can be effectively tested for defects. Their role is crucial in preventing costly post-production errors and maintaining high product reliability.

What are the key skills and qualifications needed to thrive as a DFT manager?

To excel as a DFT Manager, you need a strong background in digital design, test methodologies, and semiconductor manufacturing, often with a degree in electrical or computer engineering. Familiarity with industry-standard tools like Synopsys Tetramax, Mentor Tessent, and scripting languages, as well as experience with ATPG, BIST, and scan insertion, are typically required. Leadership, problem-solving, and effective communication are crucial soft skills for managing teams and collaborating across departments. These capabilities ensure efficient test strategies, high-quality chip designs, and successful project delivery in complex, fast-paced environments.

What are some common challenges a DFT manager faces when coordinating between design and test teams?

A DFT (Design for Test) Manager often encounters challenges in balancing the needs of the design team, who prioritize performance and area optimization, with the requirements of test engineers, who focus on maximizing test coverage and minimizing test costs. Ensuring clear communication and early involvement of DFT considerations in the design cycle is crucial to avoid costly redesigns or delays. The role also involves staying updated with the latest DFT methodologies and tools, and managing cross-functional collaboration to integrate DFT features efficiently within tight project timelines.

What is the difference between Dft Manager vs Dft Engineer?

AspectDft ManagerDft Engineer
CredentialsBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT techniquesBachelor's or Master's in Electrical/Electronic Engineering, certifications in DFT tools
Work EnvironmentOversees DFT teams, manages testing strategies, collaborates with design and manufacturingPerforms DFT design, implements test structures, analyzes test data
Industry UsageUsed in semiconductor and integrated circuit industries for testability managementUsed in semiconductor design for implementing testability features

The Dft Manager focuses on leading DFT teams and strategic planning, while the Dft Engineer is responsible for designing and implementing test features. Both roles require similar technical skills and certifications, but differ in scope and responsibilities within the semiconductor industry.

What are popular job titles related to Dft Manager jobs in Seattle, WA?

For Dft Manager jobs in Seattle, WA, the most frequently searched job titles are:

What job categories do people searching Dft Manager jobs in Seattle, WA look for?

The top searched job categories for Dft Manager jobs in Seattle, WA are:

Dft Manager jobs near you
Infographic showing various Dft Manager job openings in Seattle, WA as of August 2026, with employment types broken down into 86% Full Time, 12% Part Time, and 2% Contract. Highlights an 83% Physical, 2% Hybrid, and 15% Remote job distribution, with an average salary of $71,310 per year, or $34.3 per hour.

Principal ASIC Design Verification Engineer

K2 Space

Seattle, WA

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 21 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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