ZipRecruiter

Log In

1

Dft Jobs (NOW HIRING)

K2 Space

OR

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

191 Altera Corporation

Principal DFT Architect

San Jose, CA · On-site

$209.50 - $299.20/hr

About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next‑generation DFT architecture across Altera's most advanced FPGA, SoC ...

H R PUNDITS INC

DFT Engineers

Santa Clara, CA · On-site

$50 - $55/hr

DFT Engineers Location: Santa Clara, California Type: Contract Work Arrangement: Onsite Number of Openings: 9 & Skill Requirement Required Skills & Qualifications * 5+ years of hands-on experience in ...

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams ...

Globalfoundries

DFT Engineer

Richardson, TX

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Broadcom, Inc.

DFT Engineer

Austin, TX · On-site

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. * Perform ATPG and pattern simulation for both MBIST and scan. * Collaborate with the ...

Altera

Principal DFT Architect

San Jose, CA · On-site

$209K - $299K/yr

About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera's most advanced FPGA, SoC ...

Intel

DFT Application Engineer

Hillsboro, OR

Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...

K2 Space

Senior DFT Engineer

Seattle, WA

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Key skills for Lead ASIC DFT: please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern ...

Apple

SoC DFT Engineer

Austin, TX · On-site

Description As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and ...

Broadcom

DFT Engineer

Austin, TX · On-site

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. * Perform ATPG and pattern simulation for both MBIST and scan. * Collaborate with the ...

Mirafra Technology

DFT Engineer

Tempe, AZ

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Need knowledge of design for test (DFT) structures such as scan chains ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

Intel

DFT Application Engineer

Phoenix, AZ

Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

Role: Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to ...

previous pagenext page

Showing results 21-40

All JobsDft Jobs

Dft information

See salary details

$69.5K

$78.1K

$85K

How much do dft jobs pay per year?

As of Aug 9, 2026, the average yearly pay for dft in the United States is $78,100.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,000.00 and $82,000.00 per year, depending on experience, location, and employer.

What is a DFT job?

A DFT job typically refers to a role involving Design for Testability, where professionals develop testing strategies and procedures to ensure the quality and reliability of electronic circuits and systems. It often requires knowledge of testing tools, circuit design, and industry standards, and may involve working with automated testing equipment. The position usually demands technical skills and attention to detail to identify and address potential manufacturing defects.

Is DFT engineering a good career?

DFT engineering, which involves designing and implementing design-for-testability features in integrated circuits, is a specialized field within electronics and semiconductor industries. It offers opportunities in chip design, testing, and quality assurance, often requiring knowledge of digital design, VLSI, and testing tools. The career can be stable and well-paying for those with relevant skills and certifications, with demand driven by advancements in semiconductor technology.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is a DFT engineer?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.

Is DFT a good place to work?

DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the quality of the workplace varies and should be evaluated based on company culture, benefits, and career growth opportunities.
More about Dft jobs
What cities are hiring for Dft jobs? Cities with the most Dft job openings:
What are the most commonly searched types of Dft jobs? The most popular types of Dft jobs are:
What states have the most Dft jobs? States with the most job openings for Dft jobs include:
What job categories do people searching Dft jobs look for? The top searched job categories for Dft jobs are:
Dft jobs near you
Infographic showing various Dft job openings in the United States as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 96% In-person, and 4% Remote job distribution, with an average salary of $78,100 per year, or $37.5 per hour.

Senior DFT Engineer

K2 Space

OR

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 9 days ago

Job description

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

  • Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
  • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
  • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
  • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
  • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
  • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
  • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
  • Contribute to methodology development, automation, and flow improvements. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering or related field. 
  • 7+ years of experience in DFT for complex SoCs. 
  • Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
  • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
  • Experience with low-power DFT techniques. 
  • Familiarity with mixed-signal integration challenges and test methodologies. 
  • Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

  • Experience with MBIST/LBIST implementation and memory repair flows. 
  • Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
  • Experience with multi-voltage domain and power-aware DFT. 
  • Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
  • Scripting experience for automation. 
  • Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
  • Prior involvement in A0 silicon bring-up and yield ramp. 
  • Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

View All K2 Space Jobs

Apply