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Dft Jobs (NOW HIRING)

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California We are looking for a DFT / ATPG Engineer with strong experience in SoC/ASIC test methodologies, SCAN, MBIST, ATPG, and IJTAG implementation. The ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams ...

Altera Corporation

Principal DFT Architect

San Jose, CA · On-site

$209K - $299K/yr

About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera's most advanced FPGA, SoC ...

Wipro Limited

DFT Engineer

Santa Clara, UT · On-site

$60K - $148K/yr

DFT Engineer City: Santa Clara State/Province: California Posting Start Date: 5/20/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...

Broadcom, Inc.

DFT Engineer

Austin, TX · On-site

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. * Perform ATPG and pattern simulation for both MBIST and scan. * Collaborate with the ...

191 Altera Corporation

Principal DFT Architect

San Jose, CA · On-site

$209.50 - $299.20/hr

About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next‑generation DFT architecture across Altera's most advanced FPGA, SoC ...

New

Tanisha Systems, Inc.

ASIC DFT Engineer

Rockford, IL · On-site

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are ...

H R PUNDITS INC

DFT Engineers

Santa Clara, CA · On-site

$50 - $55/hr

DFT Engineers Location: Santa Clara, California Type: Contract Work Arrangement: Onsite Number of Openings: 9 & Skill Requirement Required Skills & Qualifications • 5+ years of hands-on experience ...

Globalfoundries

DFT Engineer

Richardson, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test solutions for semiconductor chip development. This role drives robust DFT architectures-including ATPG ...

Altera

Principal DFT Architect

San Jose, CA

$209K - $299K/yr

About the Role The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera's most advanced FPGA, SoC ...

Etched

DFT Intern

San Jose, CA · On-site

$17.50 - $23.50/hr

Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams ...

K2 Space

Senior DFT Engineer

Seattle, WA

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Broadcom

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Key skills for Lead ASIC DFT: please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern ...

Broadcom, Inc.

ASIC DFT Engineer

San Jose, CA · On-site

$141K - $226K/yr

The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing ...

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Dft information

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How much do dft jobs pay per year?

As of Jul 20, 2026, the average yearly pay for dft in the United States is $78,100.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,000.00 and $82,000.00 per year, depending on experience, location, and employer.

What is the salary of DFT engineer in Nvidia?

The salary of a DFT (Design for Test) engineer at Nvidia typically ranges from $100,000 to $150,000 annually, depending on experience, location, and specific role responsibilities. Nvidia offers competitive compensation packages that may include bonuses and stock options, especially for engineers with specialized skills in verification and testing tools.

Is DFT a good career?

A DFT (Design for Test) engineer specializes in developing testing methods for electronic devices, often requiring knowledge of circuit design and testing tools. It can be a stable career with opportunities in electronics manufacturing and semiconductor industries, especially for those with technical skills and relevant certifications. Job prospects depend on industry demand and individual expertise.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

What are ftp jobs?

FTP jobs refer to positions that involve managing or working with File Transfer Protocol (FTP) servers, which are used to transfer files over a network. These roles often require knowledge of network protocols, server management, and security practices, and may involve tasks like uploading, downloading, and maintaining files on remote servers.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) Engineer, and why are they important?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT (Design for Test) engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is DFT role?

A DFT (Design for Test) engineer is responsible for designing integrated circuits and systems to facilitate testing and fault detection. They develop test strategies, create test patterns, and ensure manufacturability and reliability of electronic components, often using specialized tools and industry standards. The role requires knowledge of digital design, testing methodologies, and sometimes automation tools.

What are DFT engineers?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.
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Dft jobs near you
Infographic showing various Dft job openings in the United States as of July 2026, with employment types broken down into 100% Contract. Highlights an 67% In-person, and 33% Remote job distribution, with an average salary of $78,100 per year, or $37.5 per hour.
DFT Engineers

DFT Engineers

Intellectt INC

Santa Clara, CA • On-site

Contractor

Re-posted 9 days ago

Job description

Hello,

I hope you're doing well

My name is Vyshu, and I’m reaching out from Intellectt Inc. regarding an exciting contract opportunity for a DFT Engineers based in Santa Clara, California with one of our prestigious clients.

I would love to connect and discuss this opportunity in more detail. Please feel free to share your updated resume at vyshnavi.t@intellectt.com

Title: DFT Engineers
Location: Santa Clara, California
Job Description:
We are looking for a DFT / ATPG Engineer with strong experience in SoC/ASIC test methodologies, SCAN, MBIST, ATPG, and IJTAG implementation. The candidate will work on DFT insertion, verification, pattern generation, coverage analysis, and debug for high-performance semiconductor designs.

Required Skills & Qualifications:
BE/B.Tech in Electronics or related field
5+ years of hands-on experience in DFT and ATPG for SoC/ASIC designs

Strong knowledge of:

  • SCAN (with SSN), MBIST, ATPG
  • DFT fundamentals (controllability, observability, scan testing)
  • Digital design and RTL concepts
  • Clock DFT and IO Test methodologies

Experience in:

  • ATPG pattern generation, debug, and coverage analysis
  • MBIST repair implementation and verification
  • DRC debug and fault model validation
  • Generating test timing and PnR collaterals
  • Expertise in IJTAG (IEEE 1687), ICL, and PDL standards

Verification experience for:

  • Boundary Scan
  • JTAG
  • SCAN
  • MBIST
  • High-Speed IO
  • ATPG
  • Familiarity with Siemens DFT tool suite and industry-standard EDA tools
  • Strong analytical, debugging, and communication skills
  • Ability to work in fast-paced semiconductor programs
 

Thanks & Regards
Vyshnavi
Recruiter
Intellectt Inc 
vyshnavi.t@intellectt.com
Direct: 732 204 6550
Desk number: 732 412 6999- Ext: 225