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Temporary Asic Rtl Design Engineer Jobs in New Jersey

... for ASIC/SoC, with track record of successful tapeouts. * Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools. * Experience with ...

Digital Design Engineer

Somerset, NJ · On-site

$143K/yr

... for ASIC/SoC, with track record of successful tapeouts. * Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools. * Experience with ...

ASIC/FPGA Design Engineer (SMES)

Camden, NJ · On-site

$111K - $151K/yr

ASIC/FPGA Design Engineer (SMES) Job Code: 34234 Job Location: Camden, NJ Schedule: 9/80 Regular ... Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate ...

FPGA/ASIC Design Engineer

Camden, NJ · On-site

$124K - $171K/yr

Job #215247 Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ. BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE) At least 3 year experience with proven ...

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Airspan Careers FPGA DESIGN ENGINEER Location: Warren, New Jersey or Plano, TX, Remote possible if ... Develop RTL designs in Verilog/System Verilog , ensuring efficient and high-performance ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Infographic showing various Temporary Asic Rtl Design Engineer job openings in New Jersey as of June 2026, with employment types broken down into 3% Locum Tenens, 56% Full Time, 17% Part Time, 7% Temporary, and 17% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution.

$143K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 3 days ago


Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ:ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more atwww.analog.comand onLinkedInandTwitter (X).

Principal Digital Design Engineer
About the Role
As a Principal Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs). You'll define product and technology roadmaps, lead architecture for mission-critical projects, and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while mentoring and developing technical talent.
Key Responsibilities

  • Develop and maintain system-level models (e.g., in SystemVerilog, or MATLAB) to analyze architectural trade-offs, verify system behavior, and inform hardware/software partitioning.
  • Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or subsystems (such as signal processing functions, control, or processor subsystems) for mixed signal ICs.
  • Collaborate closely with multi location teams such as system architects, analog designers, DV, physical design, product engineering, applications, and firmware teams to during architecture, design, evaluation, and release phases.
  • Lead design reviews, participate in specification, and ensure alignment with broader project goals.
  • Perform RTL coding (Verilog and SystemVerilog), synthesis, and lint/CDC analysis; drive designs to timing closure and area/power targets.
  • Develop and execute verification plans in collaboration with DV, including functional coverage and support for simulation/debug.
  • Analyze and resolve design, timing, and functional issues across the full digital development flow.
  • Contribute to top-level integration, including interface definition, constraint development, and support for physical implementation for functional and DFT modes.
  • Mentor and guide junior engineers, sharing expertise and promoting best practices.
  • Author and maintain clear documentation, user guides, and design collateral.
  • Stay current with industry trends and identify opportunities for process or technology improvement.
  • Perform silicon lab evaluation and debug.
  • Use Python applications to develop tests on evaluation platforms.


Must Have Skills

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of experience in digital design for ASIC/SoC, with track record of successful tapeouts.
  • Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools.
  • Experience with modeling and scripting (Matlab, TCL, Python) for design automation.
  • Strong understanding of digital design flows, timing analysis, and constraints.
  • Experience collaborating across functions (DV, PD, systems, analog/mixed-signal).
  • Excellent communication and documentation skills.
  • Demonstrated ability to lead technical projects or major design subsystems.
  • Strong understanding of business context and ability to align technical strategy with business goals

Preferred Qualifications:

  • Experience with high-speed interfaces, high speed signal processing, and low-power design.
  • Familiarity with UVM or similar verification frameworks.
  • Prior mentorship or technical leadership experience.


Preferred Education and Experience

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience
  • 12+ years of relevant experience in digital design engineering


Why You'll Love Working Here
At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.
Your expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $159,638 to $239,457.
  • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

  • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

  • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.