Altera is an independent company delivering programmable solutions that power high-performance and ... RTL experience-both board level hardware design and RTL code * Experience with board-level design ...
Altera is an independent company delivering programmable solutions that power high-performance and ... RTL experience-both board level hardware design and RTL code * Experience with board-level design ...
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$204K - $285K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$204K - $285K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$142K - $182K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$142K - $182K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$142K - $182K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Director of eSoftware Engineering - FPGA / Equities Low Latency Trading
Jersey City, NJ · On-site
$142K - $182K/yr
Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and ... Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities ...
Mechanical Engineer - MEP/HVAC
Woodcliff Lake, NJ · On-site +1
Design Engineering Market: Industrial Employment Type: Full Time Position Overview If you are ... temp controls, ventilation calculations, duct work, air handling and pipe sizing. Will review ...
Mechanical Engineer - MEP/HVAC
Woodcliff Lake, NJ · On-site +1
Design Engineering Market: Industrial Employment Type: Full Time Position Overview If you are ... temp controls, ventilation calculations, duct work, air handling and pipe sizing. Will review ...
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Warren, NJ · On-site
$141K/yr
... ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards. Key Responsibilities * Develop and implement UVM-based ...
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Warren, NJ · On-site
$141K/yr
... ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards. Key Responsibilities * Develop and implement UVM-based ...
FPGA Engineer
Moorestown, NJ · On-site
$128K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
FPGA Engineer
Moorestown, NJ · On-site
$128K - $164K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
JAva big data engineer
Jersey City, NJ · On-site
$54.75 - $70.75/hr
Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...
JAva big data engineer
Jersey City, NJ · On-site
$54.75 - $70.75/hr
Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...
JAva big data engineer
Jersey City, NJ · On-site
$54.75 - $70.75/hr
Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...
JAva big data engineer
Jersey City, NJ · On-site
$54.75 - $70.75/hr
Restful design (Restful in nature) * Model driven development * AST (Generating & Sharing) * Model ... Parse & Compile JSP, Spark B Qualifications asic Criteria * Candidates who had worked in reputed ...
Design, review, and seal engineered drawings and calculations for temporary structures such as scaffold systems, sidewalk bridges and fencing, construction hoists and personnel elevators, shoring ...
Quick apply
Design, review, and seal engineered drawings and calculations for temporary structures such as scaffold systems, sidewalk bridges and fencing, construction hoists and personnel elevators, shoring ...
Design, review, and seal engineered drawings and calculations for temporary structures such as scaffold systems, sidewalk bridges and fencing, construction hoists and personnel elevators, shoring ...
Quick apply
Design, review, and seal engineered drawings and calculations for temporary structures such as scaffold systems, sidewalk bridges and fencing, construction hoists and personnel elevators, shoring ...
Senior FPGA Development Engineer
$129K - $166K/yr
... Development Engineer to design and implement FPGA functionality using SystemVerilog for our ... not an ASIC design position. You'll join a highly collaborative, globally distributed R&D ...
Senior FPGA Development Engineer
$129K - $166K/yr
... Development Engineer to design and implement FPGA functionality using SystemVerilog for our ... not an ASIC design position. You'll join a highly collaborative, globally distributed R&D ...
Lead Infrastructure Engineer
Jersey City, NJ · On-site
$117K - $154K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
Jersey City, NJ · On-site
$117K - $154K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
$112K - $147K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
$112K - $147K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
Jersey City, NJ · On-site
$142K - $185K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
Jersey City, NJ · On-site
$142K - $185K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
$117K - $154K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Lead Infrastructure Engineer
$117K - $154K/yr
Develop and design the architecture for electronic trading systems, ensuring scalability ... Network system architecture (processor, ASIC, FPGA, port capabilities, packet forwarding, buffers ...
Senior Engineer (Bridge Design)
Carteret, NJ · On-site
$106K - $145K/yr
Possess professional Engineering license in the state of regional office * 7 - 10 years of experience in the design of permanent and or temporary engineering activities inall phases Our Investment in ...
Senior Engineer (Bridge Design)
Carteret, NJ · On-site
$106K - $145K/yr
Possess professional Engineering license in the state of regional office * 7 - 10 years of experience in the design of permanent and or temporary engineering activities inall phases Our Investment in ...
The geotechnical construction engineering focused group supports the design/analysis of temporary structures including cofferdams, gravity retaining walls such as MSE walls and soil nail walls ...
The geotechnical construction engineering focused group supports the design/analysis of temporary structures including cofferdams, gravity retaining walls such as MSE walls and soil nail walls ...
The geotechnical construction engineering focused group supports the design/analysis of temporary structures including cofferdams, gravity retaining walls such as MSE walls and soil nail walls ...
The geotechnical construction engineering focused group supports the design/analysis of temporary structures including cofferdams, gravity retaining walls such as MSE walls and soil nail walls ...
Temporary Asic Rtl Design Engineer information
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

$127K - $167K/yr
Full-time
Re-posted 7 days ago
Job description
Altera is an independent company delivering programmable solutions that power high-performance and mission-critical applications. Our FPGA technologies are widely deployed across aerospace, defense, and government systems where performance, reliability, and security are essential.
Role Overview
Altera is seeking a Customer Projects Hardware Engineer to support the Aerospace, Defense, and Government (ADG) organization. This role focuses on delivering customer-specific hardware solutions, partnering closely with defense and government customers to design, develop, and deploy FPGA-based systems for mission-critical applications.
Candidates must be located within a commutable distance of the Altera New Jersey or New Hampshire office, once the office is established.
Key Responsibilities
Design, develop, and validate hardware solutions for ADG customer projects and reference platforms
Collaborate directly with aerospace, defense, and government customers to translate system requirements into hardware architectures
Support board-level design, including schematics, layout guidance, and system integration
Lead hardware bring-up, debug, and validation in lab and customer environments
Partner with FPGA, software, and systems engineering teams to deliver end-to-end solutions
Perform signal integrity (SI), power integrity (PI), and timing analysis for high-performance, ruggedized designs
Support integration of high-speed interfaces (e.g., PCIe, Ethernet, DDR) in complex systems
Develop technical documentation, validation plans, and customer-facing design collateral
Troubleshoot system-level issues in demanding, mission-critical environments
The pay range below is for NJ or NH locations. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$134.8K- $195.1KUSD
We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.
Minimum Qualifications
Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field
6+ years of experience in hardware design, development, or system integration
RTL experience-both board level hardware design and RTL code
Experience with board-level design, schematics, and hardware bring-up/debug
Familiarity with FPGA-based systems and integration into larger platforms
Knowledge of high-speed digital design and interfaces (e.g., DDR, PCIe, Ethernet)
Hands-on lab experience using oscilloscopes, logic analyzers, and related tools
Security Clearance Requirement
This position may involve work on U.S. Government contracts that require access to controlled or classified information. Accordingly, all applicants must be eligible to obtain and maintain a U.S. Government security clearance as a condition of employment. Failure to obtain or maintain the required security clearance may result in the withdrawal of an employment offer or termination of employment, consistent with applicable law.
Preferred Qualifications
Experience supporting aerospace, defense, or government programs
Familiarity with Altera FPGA platforms and toolchain
Experience with ruggedized or mission-critical hardware design environments
Knowledge of signal integrity (SI) and power integrity (PI) analysis
Exposure to embedded systems and HW/SW co-design
Experience working in customer-facing or applications engineering roles
Key Competencies
Strong hardware debugging and system-level problem-solving skills
Ability to translate complex mission requirements into practical engineering solutions
Comfort working in customer-facing, high-visibility environments
Effective cross-functional collaboration and communication
Ability to manage multiple concurrent projects and priorities
About Altera
Sourced by ZipRecruiter
Company size
1,001 - 5,000 Employees
Headquarters location
San Jose, CA, US
Year founded
1983