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Temporary Asic Rtl Design Engineer Jobs in Texas

... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...

RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Tokyo Electron America, Inc. is seeking a ASIC Design Engineer, Senior to support the design ... Contribute to RTL and analog block design and verification to ensure proper integration.

RTL Design Engineer Location: Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural ...

RTL Design Engineer

Austin, TX

$134K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

RTL Design Engineer

Austin, TX

$134K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...

Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Posted 3 days ago


Job description

Job Title: Senior RTL Design Engineer
Location: Austin, TX (Onsite)
Duration: 11+ Months Contract

Required Qualifications

·       Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

·       8–10+ years of overall experience in ASIC/SoC Digital Design and RTL development.

·       Minimum 5+ years of hands-on experience in Verilog RTL design and development.

·       Strong understanding of digital design fundamentals, RTL design methodologies, and synthesis flows.

·       Proven experience with EDA tools for:

§  Clock Domain Crossing (CDC) analysis

§  Static Timing Analysis (STA)

§  Logic synthesis

·       Strong knowledge of AMBA AXI protocols and related system architectures.

·       Experience working with Network-on-Chip (NoC) design and integration.

·       Excellent debugging, analytical, and problem-solving skills.

·       Strong written and verbal communication skills with the ability to interact directly with customers.

 

Preferred Qualifications

§  Experience working in customer-facing engineering roles.

§  Familiarity with complete ASIC/SoC development flows.

§  Ability to work independently and manage multiple priorities in a fast-paced environment.

§  Experience collaborating with globally distributed teams.