Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Senior ASIC Design and Development Engineer
Dallas, TX · On-site
$127/hr
Senior ASIC Design and Development Engineer Location: On-Site - Dallas, TX Employment Type ... Minimum of 5 years of hands-on RTL design experience * Minimum of 5 years of experience with ...
Quick apply
Senior ASIC Design and Development Engineer
Dallas, TX · On-site
$127/hr
Senior ASIC Design and Development Engineer Location: On-Site - Dallas, TX Employment Type ... Minimum of 5 years of hands-on RTL design experience * Minimum of 5 years of experience with ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
DMTS Digital Design Engineer / Chip Lead
$206K - $410K/yr
RTL Design: Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control ... ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Senior ASIC Physical Design Engineer
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). * Define and ...
Senior ASIC Physical Design Engineer
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). * Define and ...
PCIe ASIC Design Engineer
Austin, TX · On-site
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
PCIe ASIC Design Engineer
Austin, TX · On-site
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
RTL design and implementation for ASIC/SoC development * Proficiency in Verilog/System Verilog for ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
RTL design and implementation for ASIC/SoC development * Proficiency in Verilog/System Verilog for ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
Good in understanding RTL Design and Digital concepts & Synthesis Strong experience with EDA tools ... in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at ...
Good in understanding RTL Design and Digital concepts & Synthesis Strong experience with EDA tools ... in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at ...
Design Engineer III
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Quick apply
Design Engineer III
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Temporary Asic Rtl Design Engineer information
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
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Job description
NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's motivated by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects.
What you'll be doing:
Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs.
Learn and contribute to the development and automation of flows and methodologies to efficiently build, deliver, and support a system-level IP.
Support projects by applying the performance monitoring system under the guidance of senior engineers.
Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more).
Design and implement RTL features (microarchitecture and RTL) with mentorship from experienced engineers.
Work with architects, designers, and software engineers to accomplish your tasks.
What we need to see:
Bachelor's or Master's degree in Electrical or Computer Engineering (or equivalent experience).
Strong academic background in digital design and computer architecture.
Programming experience in Python or other scripting languages.
Knowledge of RTL design (Verilog) and digital design concepts.
Understanding of basic SOC architecture concepts.
Excellent problem-solving and analytical skills.
Proven teamwork and communication across multiple teams.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993