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Temporary Asic Rtl Design Engineer Jobs (NOW HIRING)

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

... ASIC design. * Experience interacting with software, system hardware, and other cross-functional ... You will design RTL Intellectual Property (IP) with the focus on management and control subsystem ...

ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...

ASIC Engineer

San Jose, CA

$194K/yr

ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...

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Temporary Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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RTL Engineer (Ethernet)

RTL Engineer (Ethernet)

Sivaltech

San Francisco, CA • On-site

Other

Posted 29 days ago


Job description

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high-performance Networking IC development role in San Jose, CA.


Required Skills
  • Strong RTL Design experience (Verilog/SystemVerilog)
  • Hands-on with Ethernet (IEEE 802.3)
  • Experience with MAC, PCS, PHY, SerDes integration
  • Knowledge of ASIC/SoC design flow
  • Experience in clock/reset/power domain design
  • Exposure to Layer 2/3/4 protocols
  • Experience with EDA tools (Synopsys, Cadence, Mentor)

Preferred
  • Experience with 100G+ Ethernet designs
  • Knowledge of DFE, CTLE, high-speed interfaces
  • Prior experience in tape-outs/productization

Responsibilities
  • RTL design & microarchitecture development
  • Ethernet subsystem integration (MAC/PCS/SerDes)
  • Debugging and validation
  • Work with DV, PD, and firmware teams
  • Support post-silicon bring-up

Apply

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