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Contractual Asic Rtl Design Engineer Jobs in Madison, AL

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... As a senior member of our verification team, you'll understand the design & implementation with ...

... RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...

FPGA Engineer

Huntsville, AL ยท On-site

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

FPGA Engineer

Huntsville, AL ยท On-site

$128K - $164K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Participates in design reviews of and provides comments on contractor submittals on electrical ... Assists in interpreting and enforcing contractual provisions regarding contractor electrical ...

Land Systems has a long history of radar development, including hardware design, algorithm ... contractual documents, but MBSE technical oversight will be provided when needed. Each effort will ...

Land Systems has a long history of radar development, including hardware design, algorithm ... contractual documents, but MBSE technical oversight will be provided when needed. Each effort will ...

... contractual documents, but MBSE technical oversight will be provided when needed. Each effort will ... The selected candidate willinterface withprogram management and design engineers to support a ...

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Contractual Asic Rtl Design Engineer information

See Madison, AL salary details

$84.2K

$134.6K

$181K

How much do contractual asic rtl design engineer jobs pay per year?

As of Jul 15, 2026, the average yearly pay for contractual asic rtl design engineer in Madison, AL is $134,571.00, according to ZipRecruiter salary data. Most workers in this role earn between $117,800.00 and $161,300.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Madison, AL? The most popular types of Asic Rtl Design Engineer jobs in Madison, AL are:
What are popular job titles related to Contractual Asic Rtl Design Engineer jobs in Madison, AL? For Contractual Asic Rtl Design Engineer jobs in Madison, AL, the most frequently searched job titles are:
What job categories do people searching Contractual Asic Rtl Design Engineer jobs in Madison, AL look for? The top searched job categories for Contractual Asic Rtl Design Engineer jobs in Madison, AL are:
Infographic showing various Contractual Asic Rtl Design Engineer job openings in Madison, AL as of July 2026, with employment types broken down into 33% Internship, and 67% Contract. Highlights an 73% In-person, and 27% Remote job distribution, with an average salary of $134,571 per year, or $64.7 per hour.
FPGA Verification Engineer with Security Clearance

FPGA Verification Engineer with Security Clearance

Innovien Solutions

Huntsville, AL โ€ข On-site

$122K - $168K/yr

Contractor

Posted 22 days ago


Job description

FPGA VERIFICATION ENGINEER We're looking for a Secret-cleared FPGA Verification Engineer to support a confidential defense program focused on missile defense. An FPGA is a configurable chip, and this role is focused on verifying the RTL (the code that tells the chip how to behave) rather than board level design work. This is verification at the deep end, working on the actual chip. The test environment is built and the design is locked, so you skip the setup and go straight to the work that matters: running the cases and stimulus that prove the RTL behaves exactly like it has to. You will be in the SCIF with a sharp team, owning the verification that everything downstream depends on. REQUIREMENTS:
- 6+ years hands on FPGA verification, spent in functional verification rather than RTL design or board bring up
- Proven chip level verification running against completed RTL code, executing directed and constrained random test cases to prove functional behavior against the design spec (not board or card level FPGA work)
- Strong working knowledge of UVM in SystemVerilog, with the independence to build and run stimulus, triage failures, and work verification problems to resolution on their own
- Hands on Synopsys VCS for functional simulation, testbench execution, and RTL debug, comfortable driving regressions and reading coverage reports to close coverage PREFERRED SKILLS:
- Verdi for waveform analysis and debug alongside VCS, plus Vivado experience for working within the Xilinx/AMD FPGA toolchain
- Questa or ModelSim simulation experience for functional verification, testbench execution, and RTL debug
- Prior verification experience on defense, aerospace, or other cleared programs in a classified environment
- Familiarity with Lint for code quality checks and CDC (clock domain crossing) analysis to catch timing issues across asynchronous domains RESPONSIBILITIES:
- Execute directed and constrained-random test cases and stimulus against completed FPGA RTL code to verify chip-level functional behavior against design specifications
- Run functional simulations in the established VCS verification environment, analyze results, and debug failures using waveform analysis and coverage reports
- Identify, document, and work failures to resolution alongside the RTL design team, troubleshooting verification challenges as they surface
- Re-run regression suites as design changes come through to confirm fixes hold and nothing downstream breaks
- Support verification across program assemblies through the build and verification phase, including extended verification work as design changes are finalized