FPGA Engineer
$128.10K - $164.50K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$128.10K - $164.50K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
$128.10K - $164.50K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Huntsville, AL · On-site
$128.10K - $164.50K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Huntsville, AL · On-site
$128.10K - $164.50K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
Huntsville, AL · On-site +1
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
Huntsville, AL · On-site +1
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
... Design Closure, RTL and simulation assistance, system bring up and debug) * Collaborate with field and AMD Xilinx factory resources to develop and deliver technical proposals to customer project ...
Huntsville, AL · On-site
$80K - $140K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · On-site
$80K - $140K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · Remote
$90.80K - $124.40K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · Remote
$90.80K - $124.40K/yr
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Huntsville, AL · On-site
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
Huntsville, AL · On-site
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
Huntsville, AL · On-site
$175K/yr
... CPU needs for both physical and virtual server environments * Lead the design, analysis ... Serve as an engineering-level escalation resource for the Network Operations Center (NOC) and ...
New
Huntsville, AL · On-site
$175K/yr
... CPU needs for both physical and virtual server environments * Lead the design, analysis ... Serve as an engineering-level escalation resource for the Network Operations Center (NOC) and ...
New
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
Quick apply
Design, code, and debug soft real-time systems, utilizing in-depth knowledge of: * Hardware ... Optimization of CPU performance using event-driven designs instead of polling Basic Qualifications:
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
$98.50K - $206.80K/yr
Design, architect, document, and lead the development of AI/ML platform components and agentic AI ... Drive performance optimization for inference workloads (GPU/CPU scaling, model quantization ...
$36.3K - $45.9K
2% of jobs
$45.9K - $55.5K
11% of jobs
$60.6K is the 25th percentile. Wages below this are outliers.
$55.5K - $65.1K
23% of jobs
The median wage is $71.3K / yr.
$65.1K - $74.7K
22% of jobs
$74.7K - $84.3K
17% of jobs
$84.6K is the 75th percentile. Wages above this are outliers.
$84.3K - $94K
9% of jobs
$94K - $103.6K
6% of jobs
$103.6K - $113.2K
3% of jobs
$113.2K - $122.8K
3% of jobs
$122.8K - $132.4K
2% of jobs
$132.4K - $142K
1% of jobs
$36.3K
$79K
$142K
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

Apply Now
RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm
Full Time
Travel required to 10%.
Must be able to apply for and maintain a U.S. Government Security Clearance
FPGA Engineer
The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.
Key Responsibilities
FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.
Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.
Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.
Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.
Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.
System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.
Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.
Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.
Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.
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Guided missile and space vehicle manufacturing
11 - 50 Employees
Washington, DC, US
2013