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Contractual Asic Rtl Design Engineer Jobs in Missouri

EndoSec LLC

FPGA Engineer

Kansas City, MO

$122K - $157K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

EndoSec LLC

FPGA Engineer

Kansas City, MO · On-site

$126K - $163K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

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Contractual Asic Rtl Design Engineer information

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

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Principal BSP Embedded Software Engineer - Silicon Systems

Jobtailor

California, MO • On-site

$150 - $230/hr

Other

Posted 22 days ago

Job description

Responsibilities
  • Architect and own the full BSP software stack including boot ROMs, multi-level bootloaders, chip configuration, and platform initialization for custom SoCs/ASICs
  • Define and drive the security boot architecture including secure boot, chain-of-trust, hardware root-of-trust, and key management strategies
  • Design and implement power management frameworks including dynamic voltage/frequency scaling, power domain control, and low-power state transitions
  • Develop debug and trace infrastructure (CoreSight, JTAG, SWD, ETM) to support silicon bring-up and system-level debugging
  • Lead silicon bring-up activities on emulation platforms (Palladium, Zebu, Veloce), FPGA prototypes (Protium, ProFPGA, HAPS), and first silicon
  • Define HAL and driver architecture for peripheral interfaces (SPI, UART, I2C, GPIO, DMA)
  • Collaborate closely with ASIC teams to influence SoC architecture decisions and provide firmware requirements
  • Establish coding standards, review processes, and verification strategies for embedded software
  • Mentor senior and junior engineers; drive technical roadmap decisions
  • Support pre-silicon validation using emulation and RTL simulation environments
Requirements
  • B.S. in Computer Engineering, Electrical Engineering, Computer Science, or related field
  • 12+ years of experience in BSP/firmware development for SoCs or custom ASICs
  • Deep expertise in boot ROM development, multi-stage bootloader design, and chip configuration
  • Extensive experience with secure boot, cryptographic acceleration, and hardware security modules
  • Expert-level proficiency in C and C++
  • Proven experience with bare metal, RTOS (FreeRTOS, Zephyr, VxWorks), and/or embedded Linux (Yocto, Buildroot)
  • Experience with pre-silicon environments: emulation (Palladium, Zebu, Veloce) and FPGA prototyping (Protium, ProFPGA, HAPS)
  • Strong understanding of ARM/RISC-V processor architectures and SoC subsystems
  • Track record of leading silicon bring-up from emulation through production silicon
  • Ability to obtain and maintain a U.S. Security Clearance.
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