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Cpu Rtl Design Engineer Jobs in Missouri (NOW HIRING)

Jobtailor

Hardware Engineer

California, MO · On-site

$110K - $145K/yr

... CPU/GPU/network/storage industry * Experience in hardware design and validation * Experience ... Master's Degree In Electrical Engineering * PhD In Electrical Engineering Industry Keywords

EndoSec LLC

FPGA Engineer

Kansas City, MO · On-site

$122K - $157K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Data Direct Networks

Senior/Staff AI Engineer

California, MO · On-site

$93K - $128K/yr

... CPU pathways. Work on KV cache, memory, storage, and throughput bottlenecks. Design and scale ... Solve engineering problems at the intersection of AI, high-performance systems, and distributed ...

EndoSec LLC

FPGA Engineer

Kansas City, MO · On-site

$126K - $163K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

DDN

Senior Staff Engineer - AI Data Path

California, MO · On-site

$94K - $128K/yr

Lead the design and implementation of high-performance data movement pipelines using NVIDIA NIXL ... CPU, and storage tiers. * Architect and drive integration of DDN Infinia with GPU-accelerated ...

Wipro Limited

Site Relablity Engineer

O Fallon, MO · On-site

$45K - $110K/yr

Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and ... heap dumps, CPU/memory analysis, thread dumps). o Load balancers and application firewalls. o ...

Wipro Limited

Site Relablity Engineer

O Fallon, MO · On-site

$45K - $110K/yr

Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and ... heap dumps, CPU/memory analysis, thread dumps). o Load balancers and application firewalls. o ...

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Cpu Rtl Design Engineer information

See Missouri salary details

$38K

$82.7K

$148.7K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for cpu rtl design engineer in Missouri is $82,685.00, according to ZipRecruiter salary data. Most workers in this role earn between $63,800.00 and $92,400.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Missouri?

For Cpu Rtl Design Engineer jobs in Missouri, the most frequently searched job titles are:

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What cities in Missouri are hiring for Cpu Rtl Design Engineer jobs?

Cities in Missouri with the most Cpu Rtl Design Engineer job openings:

Cpu Rtl Design Engineer jobs near you

Physical Design Engineer Intern, MS

California, MO • On-site

Jobtailor
See more jobs at Jobtailorexternal

$121K - $125K/yr

Other

Posted 5 days ago

Job description

  • Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry-standard EDA tools
  • Write Python, TCL, Perl, and Shell scripts to support design and development activities
  • Analyze, debug, and implement fixes for design violations using CAD tools
  • Collaborate with RTL, synthesis, and other design teams to resolve congestion and timing bottlenecks
  • Ensure designs converge and integrate in a timely manner
Requirements
  • Currently enrolled in a Master's Degree in Electrical Engineering, Computer Engineering, or a related field
  • Expected graduation date between Fall 2027 and Summer 2028
  • Completed coursework in VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
  • Proficiency in Python, TCL, Perl, and Shell
  • Experience working in a Unix-type environment
  • Experience using Synopsys PrimeTime, Cadence Tempus, and Mentor tools
  • Strong analysis, problem-solving, and communication skills
  • Must be eligible to access export-controlled information under U.S. law; applicants may be subject to export license review
Core Competencies

Demonstrates expertise in synthesis, floor planning, and timing analysis using EDA tools, alongside proficiency in scripting languages such as Python, TCL, Perl, and Shell. Strong analytical and problem-solving skills are essential for resolving design violations and ensuring timely integration of complex logic blocks.

Highest-signal resume keywords
  • Synthesis
  • Timing Analysis
  • Python Programming
  • Synopsys PrimeTime
  • Cadence Tempus
Hard Skills
  • Synthesis
  • Floor Planning
  • Place And Route
  • Clock Insertion
  • Timing Analysis
  • Python Programming
  • TCL Programming
  • Perl Programming
  • Shell Scripting
  • Static Timing Analysis
Soft Skills
  • Analysis
  • Problem-Solving
  • Communication
Industry Keywords
  • VLSI
  • Digital Logic
  • Circuit Design
  • Computer Architecture
  • RTL Synthesis
  • Verilog
  • SystemVerilog
  • Digital Systems
  • Microelectronics
  • Export-Controlled Information
Tools & Technologies
  • EDA Tools
  • CAD Tools
  • Unix Environment
  • Mentor Tools
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