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Director Rtl Design Jobs in Missouri (NOW HIRING)

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IP Design Verification Engineer

California, MO · On-site

$110 - $170/hr

Directed/constrained random test generation in UVM * Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology * Run RTL ...

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IP Design Verification Engineer

California, MO • On-site

Jobtailor
See more jobs at Jobtailorexternal

$110 - $170/hr

Other

Posted 20 days ago

Job description

Responsibilities
  • Test bench development
  • Directed/constrained random test generation in UVM
  • Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
  • Run RTL and gate level functional verification, debug failures, and analyze coverage
  • Support mixed‑signal verification using Verilog models of analog IP
Requirements
  • Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
  • IP or SoC verification experience using System Verilog/UVM
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
  • Implementation of verification environments that include use of constrained-random stimulus
  • Code/Functional Coverage analysis
  • Writing System Verilog Assertions (SVA)
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