1

Asic Dft Engineer Jobs in California (NOW HIRING)

Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're ...

This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-generation semiconductor products. KEY RESPONSIBILITIES * Design and implement DFT ...

DFT Engineer

Santa Clara, CA · On-site

$65 - $130/hr

We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team. In this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions ...

DFT Engineer

Santa Clara, CA · On-site

$65 - $130/hr

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite ... Design and implement DFT architecture for ASIC and SoC designs. * Develop and integrate Scan ...

DFT Engineer

Palo Alto, CA · On-site

$160 - $230/hr

A Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing ...

Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle. Skills & Experience * 7+ years of handson ...

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field * 3+ years ...

DFT Engineer

Sunnyvale, CA · On-site

$140 - $210/hr

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting ... Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes. * Core ...

Showing results 21-40

Asic Dft Engineer information

What is the difference between Asic Dft Engineer vs Asic Verification Engineer?

AspectAsic Dft EngineerAsic Verification Engineer
Primary FocusDesign for Testability (DFT) implementation and validationFunctional verification of ASIC designs
Skills & CertificationsRTL design, DFT tools, scripting languagesHardware description languages, verification methodologies
Work EnvironmentDesign teams, DFT tool suitesVerification environments, simulation tools
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics design companies

While both roles are integral to ASIC development, Asic Dft Engineers focus on ensuring designs are testable and manufacturable, whereas Asic Verification Engineers concentrate on verifying the correctness of the design before fabrication.

What job categories do people searching Asic Dft Engineer jobs in California look for?

The top searched job categories for Asic Dft Engineer jobs in California are:

What cities in California are hiring for Asic Dft Engineer jobs?

Cities in California with the most Asic Dft Engineer job openings:

Infographic showing various Asic Dft Engineer job openings in California as of August 2026, with employment types broken down into 91% Full Time, 6% Part Time, and 3% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution.

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Palo Alto, CA • On-site

$175K - $280K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 7 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 151 frontline employees who took The Breakroom Quiz

16th of 72 rated aerospace companies


Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC DFT ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
  • Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
  • Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
  • Run and debug non-timing and SDF annotated gate-level simulations
  • Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or physics
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

PREFERRED SKILLS AND EXPERIENCE:
  • Master's or PhD in electrical engineering, computer engineering, physics, or related engineering field
  • Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
  • Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
  • Experience collaborating with cross-functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
  • Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent
  • Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably using Siemens Tessent tools
  • Hands-on experience with Tessent Streaming Scan Network
  • Experience with cell-aware fault models in ATPG
  • Excellent problem-solving skills, with the ability to analyze complex test failures and implement corrective actions
  • Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
  • Ability to work in a fast-paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:
Pay Range:
DFT Engineer/Senior: $175,000.00 - $280,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

What SpaceX employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


SpaceX logo

About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US