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New Grad Asic Design Verification Engineer Jobs (NOW HIRING)

AvicenaTech

ASIC Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing ... New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

K2 Space

ASIC Design Verification Engineer

$130K - $200K/yr

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Apex Informatics

ASIC Design Verification Engineer

$139K - $169K/yr

Drive Design Verification to closure using defined verification metrics for test plans, functional ... Bachelor's degree in Computer Science, Computer Engineering, or a related technical field, or ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

... this new era demands a fundamentally different class of spacecraft. Engineered to survive the ... The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the ...

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All JobsNew Grad Asic Design Verification Engineer Jobs

New Grad Asic Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do new grad asic design verification engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for new grad asic design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What does a New Grad ASIC Design Verification Engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a New Grad ASIC Design Verification Engineer, and why are they important?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC Design Verification Engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
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New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 24% Full Time, 71% Part Time, 2% Temporary, and 3% Contract. Highlights an 76% Physical, and 24% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

ASIC Design Verification Engineer

AvicenaTech

Sunnyvale, CA • On-site

$159K - $194K/yr

Full-time

Posted 27 days ago

Job description

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)
About the role:
Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.
Responsibilities:
  • Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).
  • Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.
  • Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.
  • Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.
  • Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.
  • Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency.
  • Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.
  • Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.

Qualifications:
  • Required:
    • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
    • Experience: 3+ years of professional experience in ASIC/SoC design verification.
    • UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.
    • Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.
    • Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
    • Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis.
    • Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.
  • Preferred (Nice to Have):
    • Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.
    • Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.
    • Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).
    • Familiarity with low-power verification techniques.
    • Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding.
    • Exposure to physical layer (PHY) or mixed-signal verification concepts.

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