ZipRecruiter

Log In

1

New Grad Asic Design Verification Engineer Jobs in Missouri

Jobtailor

Senior ASIC Design Engineer

California, MO · On-site

$168 - $310.50/hr

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking Senior ASIC Design ... Craft micro‑architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...

Jobtailor

IP Design Verification Engineer

California, MO · On-site

$110 - $170/hr

Closely working with design team to review specifications and architecture, define verification ... Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience ...

Jobtailor

SoC Verification Engineer

California, MO · On-site

$120 - $180/hr

Execute verification plans, including emulation and system simulation models, to ensure design ... Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to ...

Jobtailor

ASIC DFx & Test Architect Lead

California, MO · On-site

$150 - $230/hr

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. * Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals ...

Jobtailor

GPU Hardware Program Manager

California, MO · On-site

$120 - $180/hr

Identify and drive resolution of program issues and conflicts across engineering groups through ... Experience with ASIC design, silicon validation and IP development process * Familiarity with ...

next page

Showing results 1-20

All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in Missouri

New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are popular job titles related to New Grad Asic Design Verification Engineer jobs in Missouri?

For New Grad Asic Design Verification Engineer jobs in Missouri, the most frequently searched job titles are:

What job categories do people searching New Grad Asic Design Verification Engineer jobs in Missouri look for?

The top searched job categories for New Grad Asic Design Verification Engineer jobs in Missouri are:

What cities in Missouri are hiring for New Grad Asic Design Verification Engineer jobs?

Cities in Missouri with the most New Grad Asic Design Verification Engineer job openings:

New Grad Asic Design Verification Engineer jobs near you

Senior ASIC Design Verification Engineer - LPU

NVIDIA Gruppe

California, MO • On-site

$168 - $264.50/hr

Other

Posted 4 days ago

Job description

NVIDIA is transforming computer graphics, PC gaming, and accelerated computing for more than 25 years, and is now leveraging AI to define the next era of computing. The company seeks to build its next-generation inference accelerator and looks for experts to help deliver high‑performance processors.

Responsibilities
  • Verify the design and implementation of the inference accelerator as a key member of the ASIC Verification team.
  • Verify the ASIC design, architecture, reference models, and micro‑architecture using advanced verification methodologies.
  • Understand unit design and implementation, define verification scope, develop verification infrastructure, and verify design correctness.
  • Collaborate with architects, designers, and pre‑ and post‑silicon verification teams to accomplish tasks.
  • Implement and optimize automated verification flows to improve productivity and efficiency.
  • Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.
Qualifications
  • Bachelor's Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience) and 8+ years of relevant industry experience.
  • Background with building block and SoC‑level testbenches, strong debugging and analytical skills.
  • Experience with random stimulus, functional coverage, assertion‑based verification methodologies and tools.
  • Expertise in SystemVerilog and Universal Verification Methodology (UVM).
  • Experience with design and verification tools such as VCS, Verdi, or equivalent.
  • Background in UPF power verification is a plus.
  • Experience with netlist and DFT verification is a plus.
  • Programming experience in Perl, Python, or C/C++ is desirable.
  • Knowledge of ASIC design flow, from specification to GDS.
  • Knowledge of applying machine learning to ASIC verification flow.

Competitive salaries and a generous benefits package. Base salary ranges from 168,000USD to 264,500USD for Level4 and 196,000USD to 310,500USD for Level5, depending on location and experience. Candidates will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and is a proud equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.

#J-18808-Ljbffr

Apply