2

Entry Level Asic Rtl Design Engineer Jobs in Seattle, WA

FPGA Engineer

Seattle, WA ยท On-site

$147K - $190K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Overview At Ardurra , we don't just design projects--we design futures. As an Entry-Level Civil Engineer , you'll work on meaningful projects that improve lives, from sustainable water systems to ...

Overview At Ardurra , we don't just design projects-we design futures. As an Entry-Level Civil Engineer , you'll work on meaningful projects that improve lives, from sustainable water systems to ...

Overview At Ardurra , we don't just design projects--we design futures. As an Entry-Level Civil Engineer , you'll work on meaningful projects that improve lives, from sustainable water systems to ...

We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Simulate/model RF front-end systems, working with system architects, modem/DSP and ASIC engineers ...

next page

Showing results 1-20

Entry Level Asic Rtl Design Engineer information

See Seattle, WA salary details

$107K

$170.9K

$229.9K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for entry level asic rtl design engineer in Seattle, WA is $170,926.00, according to ZipRecruiter salary data. Most workers in this role earn between $149,600.00 and $204,800.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Seattle, WA? The most popular types of Asic Rtl Design Engineer jobs in Seattle, WA are:
What are popular job titles related to Entry Level Asic Rtl Design Engineer jobs in Seattle, WA? For Entry Level Asic Rtl Design Engineer jobs in Seattle, WA, the most frequently searched job titles are:
What job categories do people searching Entry Level Asic Rtl Design Engineer jobs in Seattle, WA look for? The top searched job categories for Entry Level Asic Rtl Design Engineer jobs in Seattle, WA are:
What cities near Seattle, WA are hiring for Entry Level Asic Rtl Design Engineer jobs? Cities near Seattle, WA with the most Entry Level Asic Rtl Design Engineer job openings:
Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Seattle, WA as of July 2026, with employment types broken down into 88% Full Time, 6% Part Time, 1% Temporary, 3% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $170,926 per year, or $82.2 per hour.
FPGA Engineer

FPGA Engineer

EndoSec LLC

Seattle, WA โ€ข On-site

$147K - $190K/yr

Full-time

Re-posted 6 days ago


Job description

EOE Statement
We are an equal employment opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status or any other characteristic protected by law.
Description
Apply Now
RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm
Full Time
Travel required to 10%.
Must be able to apply for and maintain a U.S. Government Security Clearance
FPGA Engineer
The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.
Key Responsibilities
FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.
Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.
Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.
Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.
Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.
System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.
Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.
Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.
Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.
Position Requirements
Position Requirements
- Ability to obtain and maintain a US government security clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- Experience developing FPGA projects and IP cores from concept to deployment, including design, simulation, testing, optimization, release, and maintenance
- Proficiency with FPGA design tools (Vivado, Quartus Prime), hardware description languages (VHDL, Verilog), hardware simulation software (GHDL, Questa)
- Experience working with programmable SoCs and development platforms from Xilinx or Intel (Versal, Zynq, Agilex, Stratix) and implementing communication between software and hardware
- Strong programming skills in scripting languages (Python, Tcl) and C/C++ for hardware/software integration
- Experience implementing standard IP core interfaces (AXI, ACE, Avalon)
- Strong analytical and problem-solving skills, with the ability to manage complex hardware design issues effectively
- Hands-on experience with hardware testing, instrumentation, and debugging tools (ILA, VIO)
- Strong documentation skills and the ability to convey complex information clearly and effectively
- Collaborative mind-set and excellent communication skills to work effectively with cross-functional teams
Preferred Qualifications
- Advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, or a related field
- Knowledge of cryptographic algorithms and experience implementation mathematical algorithms in hardware
- Experience in hardware security, tamper detection, and anti-reverse engineering techniques
- Experience with hardware acceleration techniques for computationally intensive tasks
- Familiarity with Python-based FPGA verification tools (cocotb, pyuvm)
Full-Time/Part-Time
Full-Time
This position is currently accepting applications.

EndoSec logo

About EndoSec

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Washington, DC, US

Year founded

2013