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Ai Chip Design Rtl Jobs in Seattle, WA (NOW HIRING)

... RTL, and deliver a fully verified, synthesis and timing clean block. * Collaborate with chip ... NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive ...

Senior Applied AI Engineer

Seattle, WA

$118K - $163K/yr

As part of Nvidia's applied AI team for chip design, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of the chip industry. Our team operates at the ...

You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Support chip bring‑up and debug through close collaboration with post‑silicon and test teams.

New

... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ... Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ...

... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

New

Senior ASIC Emulation Engineer

Seattle, WA · On-site

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ...

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Showing results 1-20

Ai Chip Design Rtl information

See Seattle, WA salary details

$91.6K

$158.6K

$207.7K

How much do ai chip design rtl jobs pay per year?

As of Aug 10, 2026, the average yearly pay for ai chip design rtl in Seattle, WA is $158,604.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $154,800.00 per year, depending on experience, location, and employer.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What job categories do people searching Ai Chip Design Rtl jobs in Seattle, WA look for? The top searched job categories for Ai Chip Design Rtl jobs in Seattle, WA are:
What cities near Seattle, WA are hiring for Ai Chip Design Rtl jobs? Cities near Seattle, WA with the most Ai Chip Design Rtl job openings:
Infographic showing various Ai Chip Design Rtl job openings in Seattle, WA as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 89% In-person, and 11% Remote job distribution, with an average salary of $158,604 per year, or $76.3 per hour.

Research Engineer, AI for Chip Design

International Recruiting LLC

Bellevue, WA

Full-time

Posted 13 days ago


Job description

Full-time · On-site · San Jose, CA · Austin, TX or Taiwan

About Agentrys

Agentrys is building the next generation of design automation for the semiconductor industry.

Our mission is to enable every engineering organization to build its own self-improving agentic design workforce. Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows.

Our team brings deep experience in artificial intelligence, electronic design automation, semiconductor design, GPU-accelerated computing, and production software systems. We work closely with leading semiconductor companies to turn advanced research into technology that improves engineering productivity, design quality, and time to market.

The Role

We are looking for an exceptional Research Engineer to develop new technologies at the intersection of artificial intelligence, agentic systems, GPU-accelerated computing, and Electronic Design Automation.

You will identify important research problems, develop novel algorithms and agent-native tools, build working prototypes, and help deploy them in real semiconductor design environments. Your work may span AI agents, large language models, reinforcement learning, optimization, GPU-accelerated algorithms, verification, analog design, and other areas of chip design automation.

This role is ideal for someone who combines strong research ability with exceptional implementation skills and wants to see their ideas used in production—not remain only in papers or prototypes.

What You'll Do

  • Develop new AI and agentic methods for semiconductor design and verification.

  • Build novel agent-native tools and algorithms designed specifically for autonomous engineering workflows, rather than adapting interfaces built primarily for human users.

  • Develop GPU-accelerated algorithms for computationally intensive design, analysis, search, simulation, and optimization problems.

  • Create tools that expose design state, constraints, actions, feedback, and optimization objectives in forms that agents can reason over and use effectively.

  • Build agents that can understand engineering objectives, use EDA tools, execute multi-step workflows, analyze results, recover from failures, and improve over time.

  • Research and implement techniques involving large language models, reinforcement learning, parallel algorithms, search, optimization, program synthesis, and machine learning for engineering systems.

  • Develop solutions for workflows such as functional verification, analog and custom design, RTL development, synthesis, timing analysis, and physical design.

  • Design rigorous evaluation methods for engineering agents, including problems where design data is private, sparse, or customer-specific.

  • Translate promising research ideas into reliable, scalable product capabilities.

  • Integrate AI systems with simulators, formal tools, design databases, commercial EDA tools, GPU computing platforms, and customer engineering infrastructure.

  • Work directly with semiconductor engineers to understand complex workflows and identify high-impact automation opportunities.

  • Collaborate with research, product, platform, and solutions teams across San Jose, Austin, and Taiwan.

  • Contribute to patents, publications, technical presentations, and the broader development of Agentic Design Automation.

What We're Looking For

  • PhD or master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

  • Strong programming skills in Python and proficiency in at least one systems language such as C++ or Rust.

  • Experience with machine learning frameworks such as PyTorch or JAX.

  • Demonstrated research or engineering experience in one or more of the following:

  • Electronic Design Automation

  • Semiconductor design or verification

  • Agentic AI or large language models

  • GPU-accelerated or parallel algorithms

  • Reinforcement learning

  • Combinatorial optimization

  • Program synthesis or code generation

  • Formal methods

  • Machine learning for engineering or scientific applications

  • Ability to take an ambiguous technical problem from initial formulation through experimentation, implementation, and evaluation.

  • Strong analytical, software engineering, optimization, and debugging skills.

  • High ownership, intellectual curiosity, and willingness to work across research and product boundaries.

  • Clear written and verbal communication skills.

Particularly Valuable Experience

  • Publications in leading EDA, AI, machine learning, systems, high-performance computing, or computer architecture venues.

  • Experience developing new EDA algorithms, optimization engines, design representations, or domain-specific tools.

  • Experience developing GPU-accelerated algorithms using CUDA, Triton, or related parallel-computing technologies.

  • Experience profiling and optimizing computational workloads across CPUs and GPUs.

  • Experience designing tools or environments for use by autonomous agents.

  • Experience with simulation, verification, synthesis, timing analysis, physical design, analog design, or layout.

  • Experience building agents that interact with tools, codebases, databases, or external environments.

  • Experience with LLM training, post-training, fine-tuning, retrieval, tool use, or evaluation.

  • Familiarity with Verilog, SystemVerilog, assertions, SPICE, TCL, or semiconductor design flows.

  • Experience with commercial EDA tools or production chip-design environments.

  • Experience deploying AI systems in enterprise or security-sensitive environments.

  • A strong record of implementation through research systems, open-source projects, production software, or technical competitions.

Why Agentrys

At Agentrys, you will have the opportunity to:

  • Help define a new category of semiconductor design technology.

  • Invent the agent-native algorithms and tools that will form the foundation of future automated design workflows.

  • Develop GPU-accelerated algorithms that make previously impractical design and optimization workflows possible.

  • Build AI systems that perform complex, consequential engineering work—not just generate recommendations.

  • Work with real semiconductor workflows, tools, and private engineering knowledge.

  • See your research deployed directly with leading chip-design organizations.

  • Work in a small, highly technical team where individual contributions can shape the product and company.

  • Collaborate with colleagues across San Jose, Austin, and Taiwan.

  • Change how chips are designed, rather than focus on only one design or one point tool.