Develop solutions for workflows such as functional verification, analog and custom design, RTL ... chip-design environments. * Experience deploying AI systems in enterprise or security-sensitive ...
Quick apply
Develop solutions for workflows such as functional verification, analog and custom design, RTL ... chip-design environments. * Experience deploying AI systems in enterprise or security-sensitive ...
Quick apply
Develop solutions for workflows such as functional verification, analog and custom design, RTL ... chip-design environments. * Experience deploying AI systems in enterprise or security-sensitive ...
... RTL, and deliver a fully verified, synthesis and timing clean block. * Collaborate with chip ... NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive ...
... RTL, and deliver a fully verified, synthesis and timing clean block. * Collaborate with chip ... NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive ...
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Quick apply
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Seattle, WA · On-site
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.
Seattle, WA · On-site
$170K - $250K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Seattle, WA · On-site
$170K - $250K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
$118K - $163K/yr
As part of Nvidia's applied AI team for chip design, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of the chip industry. Our team operates at the ...
$118K - $163K/yr
As part of Nvidia's applied AI team for chip design, you will have the opportunity to tap into the unlimited potential of AI and change the landscape of the chip industry. Our team operates at the ...
Seattle, WA · On-site
$190 - $280/hr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Support chip bring‑up and debug through close collaboration with post‑silicon and test teams.
New
Seattle, WA · On-site
$190 - $280/hr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Support chip bring‑up and debug through close collaboration with post‑silicon and test teams.
New
Seattle, WA · On-site
$156K - $219K/yr
... chip (SoC) platforms. * Support integration and hardware bring-up, including lab testing, debug ... Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog. * Experience implementing ...
Seattle, WA · On-site
$156K - $219K/yr
... chip (SoC) platforms. * Support integration and hardware bring-up, including lab testing, debug ... Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog. * Experience implementing ...
Seattle, WA · On-site
$170K - $250K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Quick apply
Seattle, WA · On-site
$170K - $250K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$190K - $285K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Seattle, WA · On-site
$190K - $285K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Seattle, WA · On-site
$170K - $250K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$170K - $250K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$156K - $219K/yr
... chip (SoC) platforms. * Support integration and hardware bring-up, including lab testing, debug ... Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog. * Experience implementing ...
Seattle, WA · On-site
$156K - $219K/yr
... chip (SoC) platforms. * Support integration and hardware bring-up, including lab testing, debug ... Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog. * Experience implementing ...
$170K - $250K/yr
... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ... Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ...
$170K - $250K/yr
... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ... Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ...
Seattle, WA · On-site
$130 - $200/hr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
New
Seattle, WA · On-site
$130 - $200/hr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
New
... AI data centers. Role Summary The company is seeking a highly skilled Datacenter Compute SoC ... Design, develop, and maintain cycle-accurate and transaction-level performance models using C++ and ...
Quick apply
... AI data centers. Role Summary The company is seeking a highly skilled Datacenter Compute SoC ... Design, develop, and maintain cycle-accurate and transaction-level performance models using C++ and ...
Redmond, WA · On-site
$145K - $195K/yr
RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic environment with changing needs and requirements ADDITIONAL REQUIREMENTS: * Ability to work extended ...
Redmond, WA · On-site
$145K - $195K/yr
RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic environment with changing needs and requirements ADDITIONAL REQUIREMENTS: * Ability to work extended ...
Seattle, WA · On-site
$190K - $285K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Quick apply
Seattle, WA · On-site
$190K - $285K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$190K - $285K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$190K - $285K/yr
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...
Seattle, WA · On-site
$170K - $250K/yr
You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ...
Seattle, WA · On-site
$170K - $250K/yr
You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on ...
$91.6K - $102.2K
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$144.4K - $154.9K
57% of jobs
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$207.7K
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

Full-time
Posted 13 days ago
Full-time · On-site · San Jose, CA · Austin, TX or Taiwan
About Agentrys
Agentrys is building the next generation of design automation for the semiconductor industry.
Our mission is to enable every engineering organization to build its own self-improving agentic design workforce. Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows.
Our team brings deep experience in artificial intelligence, electronic design automation, semiconductor design, GPU-accelerated computing, and production software systems. We work closely with leading semiconductor companies to turn advanced research into technology that improves engineering productivity, design quality, and time to market.
The Role
We are looking for an exceptional Research Engineer to develop new technologies at the intersection of artificial intelligence, agentic systems, GPU-accelerated computing, and Electronic Design Automation.
You will identify important research problems, develop novel algorithms and agent-native tools, build working prototypes, and help deploy them in real semiconductor design environments. Your work may span AI agents, large language models, reinforcement learning, optimization, GPU-accelerated algorithms, verification, analog design, and other areas of chip design automation.
This role is ideal for someone who combines strong research ability with exceptional implementation skills and wants to see their ideas used in production—not remain only in papers or prototypes.
What You'll Do
Develop new AI and agentic methods for semiconductor design and verification.
Build novel agent-native tools and algorithms designed specifically for autonomous engineering workflows, rather than adapting interfaces built primarily for human users.
Develop GPU-accelerated algorithms for computationally intensive design, analysis, search, simulation, and optimization problems.
Create tools that expose design state, constraints, actions, feedback, and optimization objectives in forms that agents can reason over and use effectively.
Build agents that can understand engineering objectives, use EDA tools, execute multi-step workflows, analyze results, recover from failures, and improve over time.
Research and implement techniques involving large language models, reinforcement learning, parallel algorithms, search, optimization, program synthesis, and machine learning for engineering systems.
Develop solutions for workflows such as functional verification, analog and custom design, RTL development, synthesis, timing analysis, and physical design.
Design rigorous evaluation methods for engineering agents, including problems where design data is private, sparse, or customer-specific.
Translate promising research ideas into reliable, scalable product capabilities.
Integrate AI systems with simulators, formal tools, design databases, commercial EDA tools, GPU computing platforms, and customer engineering infrastructure.
Work directly with semiconductor engineers to understand complex workflows and identify high-impact automation opportunities.
Collaborate with research, product, platform, and solutions teams across San Jose, Austin, and Taiwan.
Contribute to patents, publications, technical presentations, and the broader development of Agentic Design Automation.
What We're Looking For
PhD or master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Strong programming skills in Python and proficiency in at least one systems language such as C++ or Rust.
Experience with machine learning frameworks such as PyTorch or JAX.
Demonstrated research or engineering experience in one or more of the following:
Electronic Design Automation
Semiconductor design or verification
Agentic AI or large language models
GPU-accelerated or parallel algorithms
Reinforcement learning
Combinatorial optimization
Program synthesis or code generation
Formal methods
Machine learning for engineering or scientific applications
Ability to take an ambiguous technical problem from initial formulation through experimentation, implementation, and evaluation.
Strong analytical, software engineering, optimization, and debugging skills.
High ownership, intellectual curiosity, and willingness to work across research and product boundaries.
Clear written and verbal communication skills.
Particularly Valuable Experience
Publications in leading EDA, AI, machine learning, systems, high-performance computing, or computer architecture venues.
Experience developing new EDA algorithms, optimization engines, design representations, or domain-specific tools.
Experience developing GPU-accelerated algorithms using CUDA, Triton, or related parallel-computing technologies.
Experience profiling and optimizing computational workloads across CPUs and GPUs.
Experience designing tools or environments for use by autonomous agents.
Experience with simulation, verification, synthesis, timing analysis, physical design, analog design, or layout.
Experience building agents that interact with tools, codebases, databases, or external environments.
Experience with LLM training, post-training, fine-tuning, retrieval, tool use, or evaluation.
Familiarity with Verilog, SystemVerilog, assertions, SPICE, TCL, or semiconductor design flows.
Experience with commercial EDA tools or production chip-design environments.
Experience deploying AI systems in enterprise or security-sensitive environments.
A strong record of implementation through research systems, open-source projects, production software, or technical competitions.
Why Agentrys
At Agentrys, you will have the opportunity to:
Help define a new category of semiconductor design technology.
Invent the agent-native algorithms and tools that will form the foundation of future automated design workflows.
Develop GPU-accelerated algorithms that make previously impractical design and optimization workflows possible.
Build AI systems that perform complex, consequential engineering work—not just generate recommendations.
Work with real semiconductor workflows, tools, and private engineering knowledge.
See your research deployed directly with leading chip-design organizations.
Work in a small, highly technical team where individual contributions can shape the product and company.
Collaborate with colleagues across San Jose, Austin, and Taiwan.
Change how chips are designed, rather than focus on only one design or one point tool.
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Recruiting and staffing services
51 - 200 Employees
Bellevue, WA, US
2014