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Ai Chip Design Rtl Jobs in Seattle, WA (NOW HIRING)

Senior Silicon Engineer

Redmond, WA · On-site

$117K - $160K/yr

... AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA. • ... Preferred Qualifications: • 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP ...

Communications Specialist, Chips, Amazon

Seattle, WA · On-site

$60K - $80K/yr

... AI workloads at unprecedented scale. We're seeking a communications professional to join our team ... semiconductor design and advanced computing hardware. You'll help translate chip architecture ...

... for AI and accelerated computing. We are constantly looking for ways to improve our GPU ... Your role will be cross-disciplinary, working with software, ASIC design, verification, physical ...

... digital AI inference chip. We are seeking an experienced Compiler Engineer to join our exceptional team. Responsibilities: * Design and implement software that maps neural nets onto our spatial ...

Contribute to the design and implementation of embedded firmware architecture, including boot flows ... Develop device drivers for on-chip peripherals such as DMA engines, memory controllers ...

New

Senior FPGA Engineer

Seattle, WA · On-site

$132 - $220/hr

... ASIC design and verification work experience. * Proficient in writing RTL using Verilog ... Experience with common on-chip bus protocols such as AMBA (AXI, AHB, APB) * Experience with IEEE ...

... design, engineering, analytics, and retail stakeholders. * Experience applying AI to support ... RTL) languages. * Experience collaborating with agencies and systems integrators to pilot new ...

Senior Firmware Engineer, FPGA

Bellevue, WA · On-site

$134K - $178K/yr

Trusted by leading AI labs, startups, and global enterprises, CoreWeave combines superior ... FPGA development - design, implement, and maintain FPGA logic for server-class or embedded platform ...

Showing results 41-60

Ai Chip Design Rtl information

See Seattle, WA salary details

$91.6K

$158.6K

$207.7K

How much do ai chip design rtl jobs pay per year?

As of Aug 11, 2026, the average yearly pay for ai chip design rtl in Seattle, WA is $158,604.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $154,800.00 per year, depending on experience, location, and employer.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What job categories do people searching Ai Chip Design Rtl jobs in Seattle, WA look for? The top searched job categories for Ai Chip Design Rtl jobs in Seattle, WA are:
What cities near Seattle, WA are hiring for Ai Chip Design Rtl jobs? Cities near Seattle, WA with the most Ai Chip Design Rtl job openings:
Infographic showing various Ai Chip Design Rtl job openings in Seattle, WA as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 89% In-person, and 11% Remote job distribution, with an average salary of $158,604 per year, or $76.3 per hour.

Senior Silicon Engineer

Microsoft

Redmond, WA • On-site

$117K - $160K/yr

Full-time

Posted 21 days ago


Microsoft rating

8.5

Company rating: 8.5 out of 10

Based on 132 frontline employees who took The Breakroom Quiz

78th of 242 rated software companies


Job description

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Interface IP Team team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Silicon Engineer to join the team.
#SCHIE
Responsibilities
Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows.
• Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners.
• Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements.
• Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations.
• Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA.
• Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership.
Qualifications
Required Qualifications:
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
    • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
    • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
    • OR equivalent experience.

Preferred Qualifications:
• 8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
• 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
• Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
• Experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)
• Proficiency in recent synthesis tool capabilities and methods for QoR improvement
• Proficiency in static timing analysis
• Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification
• Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines
• Proficiency in translating physical design results into feedback for flow or RTL improvement
• Proficiency in Tcl, Python
Knowledge of full RTL2GDS flow
Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

Sourced by ZipRecruiter

Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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