Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
Quick apply
Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
Quick apply
Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
... Next-Gen AI SOC chip. If hired, you will be responsible for delivering TFM (tool, flow and ... and resolve design issues, and provide guidance to engineers. Qualifications Required ...
... Next-Gen AI SOC chip. If hired, you will be responsible for delivering TFM (tool, flow and ... and resolve design issues, and provide guidance to engineers. Qualifications Required ...
Seattle, WA · On-site
$230K - $322K/yr
Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ... Bachelor's degree in Electrical Engineering, or related technical discipline * 7+ years of ...
Seattle, WA · On-site
$230K - $322K/yr
Design and simulate on-chip electromagnetic (EM) structures and collaborate with the package ... Bachelor's degree in Electrical Engineering, or related technical discipline * 7+ years of ...
Seattle, WA · On-site
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Seattle, WA · On-site
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Redmond, WA · On-site
Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...
Redmond, WA · On-site
Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...
Everett, WA · On-site
$80K - $109K/yr
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue-Chip customers. In the role of ...
New
Everett, WA · On-site
$80K - $109K/yr
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue-Chip customers. In the role of ...
New
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. POWERED BY ...
New
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. POWERED BY ...
New
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Quick apply
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Redmond, WA · On-site
$160K - $225K/yr
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Redmond, WA · On-site
$160K - $225K/yr
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Redmond, WA · On-site
$160K - $225K/yr
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Redmond, WA · On-site
$160K - $225K/yr
Experience in designing multi-chip RF modules for cellular or Wi-Fi applications * Familiar with ... RFIC Design Engineer/Senior: $160,000.00 - $225,000/per year Your actual level and base salary will ...
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. The Level 1 ...
New
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. The Level 1 ...
New
Seattle, WA · On-site
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Seattle, WA · On-site
$190K - $280K/yr
Support chip bring-up and debug through close collaboration with post-silicon and test teams ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Everett, WA · On-site
$84K - $113K/yr
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue-Chip customers. In the role of ...
New
Everett, WA · On-site
$84K - $113K/yr
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue-Chip customers. In the role of ...
New
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. The Level 2 ...
New
Everett, WA · On-site
Focusing on commercial and military aircrafts, NAT provides first class services in design, engineering, quality, certification, and manufacturing for a variety of Blue Chip customers. The Level 2 ...
New
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ...
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Experience with chip-package co-design or advanced packaging (2.5D/3D). * Familiarity with physical ...
The Layout Design Engineering group is an integral part of the Silicon Engineering department ... Expert in full-chip/SOC-level floorplanning and integration -- physical implementation of cells and ...
Quick apply
The Layout Design Engineering group is an integral part of the Silicon Engineering department ... Expert in full-chip/SOC-level floorplanning and integration -- physical implementation of cells and ...
$122K - $184K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Description As part of a very dedicated team you will be at the heart of the chip design effort ...
$122K - $184K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Description As part of a very dedicated team you will be at the heart of the chip design effort ...
As Senior RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to ... Key job responsibilities Collaborate with communications systems, digital design, and chip ...
As Senior RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to ... Key job responsibilities Collaborate with communications systems, digital design, and chip ...
As Senior RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to ... Key job responsibilities Collaborate with communications systems, digital design, and chip ...
As Senior RFIC Design Engineer, you will engage with an experienced cross-disciplinary staff to ... Key job responsibilities Collaborate with communications systems, digital design, and chip ...
$46.1K - $58.3K
2% of jobs
$58.3K - $70.5K
11% of jobs
$77K is the 25th percentile. Wages below this are outliers.
$70.5K - $82.7K
23% of jobs
The median wage is $90.6K / yr.
$82.7K - $94.9K
22% of jobs
$94.9K - $107.1K
17% of jobs
$107.5K is the 75th percentile. Wages above this are outliers.
$107.1K - $119.3K
9% of jobs
$119.3K - $131.5K
6% of jobs
$131.5K - $143.8K
3% of jobs
$143.8K - $156K
3% of jobs
$156K - $168.2K
2% of jobs
$168.2K - $180.4K
1% of jobs
$46.1K
$100.3K
$180.4K
As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.
To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.
A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.
For Chip Design Engineer jobs in Seattle, WA, the most frequently searched job titles are:
The top searched job categories for Chip Design Engineer jobs in Seattle, WA are:

Full-time
Posted 19 days ago
Full-time · On-site · San Jose, CA · Austin, TX or Taiwan
About Agentrys
Agentrys is building the next generation of design automation for the semiconductor industry.
Our mission is to enable every engineering organization to build its own self-improving agentic design workforce. Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows.
Our team brings deep experience in artificial intelligence, electronic design automation, semiconductor design, GPU-accelerated computing, and production software systems. We work closely with leading semiconductor companies to turn advanced research into technology that improves engineering productivity, design quality, and time to market.
The Role
We are looking for an exceptional Research Engineer to develop new technologies at the intersection of artificial intelligence, agentic systems, GPU-accelerated computing, and Electronic Design Automation.
You will identify important research problems, develop novel algorithms and agent-native tools, build working prototypes, and help deploy them in real semiconductor design environments. Your work may span AI agents, large language models, reinforcement learning, optimization, GPU-accelerated algorithms, verification, analog design, and other areas of chip design automation.
This role is ideal for someone who combines strong research ability with exceptional implementation skills and wants to see their ideas used in production—not remain only in papers or prototypes.
What You'll Do
Develop new AI and agentic methods for semiconductor design and verification.
Build novel agent-native tools and algorithms designed specifically for autonomous engineering workflows, rather than adapting interfaces built primarily for human users.
Develop GPU-accelerated algorithms for computationally intensive design, analysis, search, simulation, and optimization problems.
Create tools that expose design state, constraints, actions, feedback, and optimization objectives in forms that agents can reason over and use effectively.
Build agents that can understand engineering objectives, use EDA tools, execute multi-step workflows, analyze results, recover from failures, and improve over time.
Research and implement techniques involving large language models, reinforcement learning, parallel algorithms, search, optimization, program synthesis, and machine learning for engineering systems.
Develop solutions for workflows such as functional verification, analog and custom design, RTL development, synthesis, timing analysis, and physical design.
Design rigorous evaluation methods for engineering agents, including problems where design data is private, sparse, or customer-specific.
Translate promising research ideas into reliable, scalable product capabilities.
Integrate AI systems with simulators, formal tools, design databases, commercial EDA tools, GPU computing platforms, and customer engineering infrastructure.
Work directly with semiconductor engineers to understand complex workflows and identify high-impact automation opportunities.
Collaborate with research, product, platform, and solutions teams across San Jose, Austin, and Taiwan.
Contribute to patents, publications, technical presentations, and the broader development of Agentic Design Automation.
What We're Looking For
PhD or master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Strong programming skills in Python and proficiency in at least one systems language such as C++ or Rust.
Experience with machine learning frameworks such as PyTorch or JAX.
Demonstrated research or engineering experience in one or more of the following:
Electronic Design Automation
Semiconductor design or verification
Agentic AI or large language models
GPU-accelerated or parallel algorithms
Reinforcement learning
Combinatorial optimization
Program synthesis or code generation
Formal methods
Machine learning for engineering or scientific applications
Ability to take an ambiguous technical problem from initial formulation through experimentation, implementation, and evaluation.
Strong analytical, software engineering, optimization, and debugging skills.
High ownership, intellectual curiosity, and willingness to work across research and product boundaries.
Clear written and verbal communication skills.
Particularly Valuable Experience
Publications in leading EDA, AI, machine learning, systems, high-performance computing, or computer architecture venues.
Experience developing new EDA algorithms, optimization engines, design representations, or domain-specific tools.
Experience developing GPU-accelerated algorithms using CUDA, Triton, or related parallel-computing technologies.
Experience profiling and optimizing computational workloads across CPUs and GPUs.
Experience designing tools or environments for use by autonomous agents.
Experience with simulation, verification, synthesis, timing analysis, physical design, analog design, or layout.
Experience building agents that interact with tools, codebases, databases, or external environments.
Experience with LLM training, post-training, fine-tuning, retrieval, tool use, or evaluation.
Familiarity with Verilog, SystemVerilog, assertions, SPICE, TCL, or semiconductor design flows.
Experience with commercial EDA tools or production chip-design environments.
Experience deploying AI systems in enterprise or security-sensitive environments.
A strong record of implementation through research systems, open-source projects, production software, or technical competitions.
Why Agentrys
At Agentrys, you will have the opportunity to:
Help define a new category of semiconductor design technology.
Invent the agent-native algorithms and tools that will form the foundation of future automated design workflows.
Develop GPU-accelerated algorithms that make previously impractical design and optimization workflows possible.
Build AI systems that perform complex, consequential engineering work—not just generate recommendations.
Work with real semiconductor workflows, tools, and private engineering knowledge.
See your research deployed directly with leading chip-design organizations.
Work in a small, highly technical team where individual contributions can shape the product and company.
Collaborate with colleagues across San Jose, Austin, and Taiwan.
Change how chips are designed, rather than focus on only one design or one point tool.
Sourced by ZipRecruiter
Recruiting and staffing services
51 - 200 Employees
Bellevue, WA, US
2014