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Asic Physical Design Jobs (NOW HIRING)

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Mundi

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next‑generation satellite and space systems. You will own the full physical ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Meta

ASIC Engineer, Physical Design

Sunnyvale, CA · On-site

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff ...

Meta

ASIC Engineer, Physical Design

Austin, TX

$178K/yr

ASIC Engineer, Physical Design Responsibilities: * Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff ...

NVIDIA Corporation

## Senior ASIC Physical Design Engineer, NetlistingApplylocations: US, CA, Santa Clara: US, TX, Austintime type: Full timeposted on: Posted Todayjob requisition id: JR2021166NVIDIA has continuously ...

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Asic Physical Design information

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$95K

$141.5K

How much do asic physical design jobs pay per year?

As of Sep 10, 2026, the average yearly pay for asic physical design in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is an ASIC Physical Design engineer?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design engineer?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

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Cities with the most Asic Physical Design job openings:

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Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in the United States as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

ASIC Physical Design Engineer

New York, NY • On-site

Jane Street
Finance and Insurance • 1 - 5K employees
Learn more about Jane Streetexternal

$148K - $153K/yr

Full-time

Re-posted 12 days ago

Job description

About the Position

We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking, and research infrastructure.

This isn't a traditional PD role. We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. 

If you've spent your career exclusively in PD, this probably isn't the right fit- but if you've worked across the stack, either because you started as an RTL designer and moved into PD, or because you were on a smaller team where you had to wear multiple hats, we'd love to talk.

We're big believers in the ability of tools to improve the productivity, reliability, and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You
  • You have 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
  • You don't need to have optimized every last detail of every flow, but you should have broad enough experience across PD that you can own a flow end-to-end and know where the risks are
  • Beyond PD, you can read and write RTL and understand how front-end design decisions affect physical implementation-and vice versa; You think about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
  • You're interested in using software engineering techniques to improve the hardware design process, and you have experience programming in a high-level language (Python, C++, Haskell, etc.)

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

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