Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Physical design team to close and sign-off timing. You will also come up with ideas and plans to ...
ASIC & FPGA Design Engineer
Orlando, FL · On-site +1
$114K - $158K/yr
You will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed Martin ... parasitic aware physical designs.You will operate in a dual tool environment (Synopsys Custom ...
ASIC & FPGA Design Engineer
Orlando, FL · On-site +1
$114K - $158K/yr
You will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed Martin ... parasitic aware physical designs.You will operate in a dual tool environment (Synopsys Custom ...
Hardware Design Engineer 3
Fort Meade, FL · On-site
$100 - $130/hr
Knowledge of physical ASIC design and fabrication including place and route tools and semiconductor manufacturing * Familiar with commercial software tools to build circuit schematics and simulate or ...
Hardware Design Engineer 3
Fort Meade, FL · On-site
$100 - $130/hr
Knowledge of physical ASIC design and fabrication including place and route tools and semiconductor manufacturing * Familiar with commercial software tools to build circuit schematics and simulate or ...
Asic Physical Design information
See Florida salary details
$71K - $74.2K
0% of jobs
$74.2K - $77.3K
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$77.3K - $80.5K
0% of jobs
$80.5K - $83.6K
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$83.6K - $86.8K
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$86.8K - $89.9K
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$89.9K - $93.1K
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$93.1K - $96.3K
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$96.3K - $99.4K
1% of jobs
$101.2K is the 25th percentile. Wages below this are outliers.
$99.4K - $102.6K
43% of jobs
The median wage is $102.9K / yr.
$102.6K - $105.7K
56% of jobs
$71K
$105.7K
How much do asic physical design jobs pay per year?
As of Aug 10, 2026, the average yearly pay for asic physical design in Florida is $104,179.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,600.00 and $104,600.00 per year, depending on experience, location, and employer.
What is the difference between Asic Physical Design vs Asic Verification Engineer?
| Aspect | Asic Physical Design | Asic Verification Engineer |
|---|---|---|
| Primary Focus | Implementing physical layout, placement, routing of ASICs | Verifying functionality and performance of ASIC designs |
| Skills & Certifications | VLSI design, EDA tools, CMOS fabrication knowledge | Hardware description languages, simulation tools, testbench development |
| Work Environment | Design teams, CAD tools, EDA software | Simulation labs, testing environments, design verification teams |
| Industry Usage | Foundries, semiconductor companies, chip design firms | ASIC design companies, semiconductor firms, EDA tool providers |
While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.
What is an ASIC Physical Design engineer?
ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.
What are the key skills and qualifications needed to thrive as an ASIC Physical Design engineer?
To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.
What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?
ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.
What are popular job titles related to Asic Physical Design jobs in Florida? For Asic Physical Design jobs in Florida, the most frequently searched job titles are:
- Rtl Design Engineer
- Asic Engineer
- Remote Work From Home Analog Mixed Signal Design Engineer
- Freelance Physical Design Engineer
- Junior Asic Verification Engineer
- Asic Design Verification Engineer
- Vice President Asic Design Engineer
- Contract Physical Design Engineer
- Work From Home Analog Mixed Signal Design Engineer
- Remote Asic Design
What job categories do people searching Asic Physical Design jobs in Florida look for? The top searched job categories for Asic Physical Design jobs in Florida are:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976