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Asic Design Verification Engineer Jobs in Florida

Apple

GPU Design Verification Engineer

Orlando, FL · On-site

$127K - $155K/yr

Experience or coursework in digital design/verification. Experience or coursework with object oriented programming languages. Experience or coursework using HDL simulators and waveform viewers. BS ...

Apple

GPU Design Verification Engineer

Orlando, FL

$127K - $155K/yr

Experience or coursework in digital design/verification. Experience or coursework with object oriented programming languages. Experience or coursework using HDL simulators and waveform viewers. BS ...

Apple

GPU Design Verification Engineer

Orlando, FL

$127K - $155K/yr

... of engineers in delivering well-verified IP. - Collaborate with architecture, design and modeling teams to converge on design specification. - Develop and drive verification plans, schedules and ...

Apple

GPU Design Verification Engineer

Orlando, FL · On-site

$127K - $155K/yr

... of engineers in delivering well-verified IP. - Collaborate with architecture, design and modeling teams to converge on design specification. - Develop and drive verification plans, schedules and ...

Apple

GPU Design Verification Engineer

Orlando, FL

$127K - $155K/yr

Description As a Graphics Core Hardware Verification Engineer, you will be tasked with the ... design specification. - Develop and drive verification plans and schedules. - Architect test ...

Apple

GPU Design Verification Engineer

Orlando, FL · On-site

$127K - $155K/yr

Description As a Graphics Core Hardware Verification Engineer, you will be tasked with the ... design specification. - Develop and drive verification plans and schedules. - Architect test ...

Sapsol Technologies Inc

FPGA Engineer

Melbourne, FL · On-site

$120K - $154K/yr

FPGA verification in lab testing and/or Hardware FPGA design verification testing * Experience with ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...

New

Sapsol Technologies Inc

FPGA Engineer

Melbourne, FL

$120K - $154K/yr

FPGA verification in lab testing and/or Hardware FPGA design verification testing * Experience with ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...

New

Lockheed Martin

ASIC & FPGA Design Engineer Stf

Orlando, FL · On-site +1

$114K - $158K/yr

You will be the ASIC & FPGA Design Engineer for the ASIC/FPGA department at Lockheed Martin ... Drive DRC, LVS and ERC verification to achieve full closure for each target process. Perform or ...

Raytheon

Senior FPGA Design Engineer

Miami, FL

$117K - $162K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Raytheon

Senior FPGA Design Engineer

Orlando, FL

$114K - $158K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

Apple

Timing Design Engineer

Melbourne, FL

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

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All JobsAsic Design Verification Engineer JobsAsic Design Verification Engineer Jobs in Florida

Asic Design Verification Engineer information

See Florida salary details

$78.8K

$111.5K

$124.8K

How much do asic design verification engineer jobs pay per year?

As of Jul 29, 2026, the average yearly pay for asic design verification engineer in Florida is $111,458.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,600.00 and $124,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by ASIC Design Verification Engineers, and how can they be overcome?

ASIC Design Verification Engineers often encounter challenges such as managing complex verification environments, ensuring thorough coverage, and keeping up with tight project deadlines. Debugging failures in large, intricate designs can be time-consuming and requires strong problem-solving skills. To overcome these challenges, engineers typically rely on robust verification methodologies (such as UVM), effective communication within cross-functional design teams, and continuous learning to stay updated with the latest verification tools and techniques. Collaboration with designers and regular code reviews also help in identifying and resolving issues early in the development cycle.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer, and why are they important?

To thrive as an ASIC Design Verification Engineer, you need a solid understanding of digital design, verification methodologies (such as UVM or OVM), and a degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (like ModelSim or VCS), and scripting languages (such as Python or Perl) is essential, along with experience using version control systems. Strong problem-solving skills, attention to detail, and effective communication are crucial for identifying design issues and collaborating with cross-functional teams. These skills ensure accurate verification, reduce time-to-market, and contribute to the delivery of reliable and high-performance ASIC products.

What does an ASIC Design Verification Engineer do?

An ASIC Design Verification Engineer is responsible for ensuring that application-specific integrated circuits (ASICs) function as intended before they are manufactured. They develop and implement verification plans, create testbenches, and run simulations to identify design errors. Their work involves using hardware description languages (HDLs) like Verilog or VHDL and tools such as UVM to systematically verify design functionality. This role is crucial for catching bugs early, reducing costly mistakes in silicon, and improving product reliability.

What is the difference between Asic Design Verification Engineer vs Asic Design Engineer?

AspectAsic Design Verification EngineerAsic Design Engineer
Primary FocusVerifying the functionality of ASIC designs through testing and simulationDesigning and developing ASIC hardware components and architecture
Skills & CertificationsKnowledge of verification tools, scripting, hardware description languages (HDL), and testing methodologiesProficiency in HDL, digital design, and circuit architecture
Work EnvironmentMostly in verification labs, simulation environments, and testing setupsDesign offices, hardware labs, and development teams
Industry UsageCommonly employed in semiconductor and electronics companies for testing ASICsUsed in chip design companies for creating hardware components

In summary, Asic Design Verification Engineers focus on testing and validating ASIC designs to ensure functionality, while Asic Design Engineers are responsible for creating and developing the ASIC hardware itself. Both roles require knowledge of HDL and are integral to the ASIC development process.

What are the most commonly searched types of Asic Design Verification Engineer jobs in Florida? The most popular types of Asic Design Verification Engineer jobs in Florida are:
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Asic Design Verification Engineer jobs near you
Infographic showing various Asic Design Verification Engineer job openings in Florida as of July 2026, with employment types broken down into 21% As Needed, 72% Full Time, 4% Part Time, 2% Contract, and 1% Summer. Highlights an 87% Physical, 7% Hybrid, and 6% Remote job distribution, with an average salary of $111,458 per year, or $53.6 per hour.
Senior FPGA/ASIC Verification Engineer

Senior FPGA/ASIC Verification Engineer

New York Technology Partners

Melbourne, FL • On-site

$96K - $129K/yr

Other

Posted 2 days ago

Job description

JOB SUMMARY:

Expert level verification engineer with strong SystemVerilog and UVM experience. As an alternative to SystemVerilog/UVM, we are open to candidates with a verification background in lab testing and/or design verification testing. Experience with design on Xilinx products would be a strong plus.

Required Skills:

  • Expert level verification engineer with strong SystemVerilog and/ or UVM experience or
  • FPGA verification in lab testing and/or Hardware FPGA design verification testing
  • Experience with design on Xilinx products would be a strong plus
  • expected to communicate effectively with emerging engineers at the offshore team, GETC I site and provide both technical and process guidance to the verification team.

Core Responsibilities

  • RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
  • Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
  • Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing.

Key Qualifications

  • Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
  • Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

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