RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Melbourne, FL · On-site
$114K - $157K/yr
FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Perform RTL coding, simulation, synthesis, place & route, and timing analysis. * Develop FPGA ...
Melbourne, FL · On-site
$114K - $157K/yr
FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Perform RTL coding, simulation, synthesis, place & route, and timing analysis. * Develop FPGA ...
$75 - $90/hr
Strong skills in RTL design (VHDL/Verilog/SystemVerilog), timing closure, and block design ... The engineer will be supporting the development of a cryptography platform and collaborate across ...
Quick apply
$75 - $90/hr
Strong skills in RTL design (VHDL/Verilog/SystemVerilog), timing closure, and block design ... The engineer will be supporting the development of a cryptography platform and collaborate across ...
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Orlando, FL · On-site
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Orlando, FL · On-site
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Orlando, FL · On-site
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Orlando, FL · On-site
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Quick apply
Our engineering excellence, based in Florida, Washington State, Washington D.C., and Hamburg ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Quick apply
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Our engineering excellence, based in Florida, Washington State, Washington D.C., Hamburg, Germany ... Design, implement and test Register-Transfer Level (RTL) features and components guided by system ...
Expert‑level verification engineer with strong SystemVerilog and UVM experience. As an ... RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
Quick apply
Expert‑level verification engineer with strong SystemVerilog and UVM experience. As an ... RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Melbourne, FL · On-site
Role: Hardware Engineer/ Electrical Engineer- FPGA Location: Melbourne, FL - Onsite Duration ... RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
Quick apply
Melbourne, FL · On-site
Role: Hardware Engineer/ Electrical Engineer- FPGA Location: Melbourne, FL - Onsite Duration ... RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
$30.3K - $38.3K
2% of jobs
$38.3K - $46.3K
11% of jobs
$50.6K is the 25th percentile. Wages below this are outliers.
$46.3K - $54.3K
23% of jobs
The median wage is $59.5K / yr.
$54.3K - $62.3K
22% of jobs
$62.3K - $70.3K
17% of jobs
$70.6K is the 75th percentile. Wages above this are outliers.
$70.3K - $78.4K
9% of jobs
$78.4K - $86.4K
6% of jobs
$86.4K - $94.4K
3% of jobs
$94.4K - $102.4K
3% of jobs
$102.4K - $110.4K
2% of jobs
$110.4K - $118.4K
1% of jobs
$30.3K
$65.9K
$118.4K
As an RTL Design Engineer, you can advance into roles such as Senior Design Engineer, Technical Lead, or even Design Manager as you gain experience and demonstrate strong technical expertise. Many professionals also transition into related areas such as verification engineering, system architecture, or product management. The role offers continuous learning opportunities and exposure to cutting-edge semiconductor technology, making it ideal for those interested in expanding their skillset. Career progression is often supported by successful project delivery, ongoing education, and active collaboration within multidisciplinary teams.
To thrive as an RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and a bachelor's or master’s degree in electrical or computer engineering. Experience with industry-standard EDA tools such as Synopsys or Cadence, and knowledge of FPGA or ASIC design flow, are typically required. Strong problem-solving, teamwork, and communication skills are essential for effective collaboration with verification teams and other engineering groups. These competencies are critical to accurately translate system requirements into robust, manufacturable hardware designs within fast-paced project timelines.
An RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like VHDL or Verilog. They develop and optimize high-performance, power-efficient designs for ASICs or FPGAs based on system requirements. Their role includes writing RTL code, performing simulations, debugging issues, and collaborating with verification, physical design, and architecture teams. RTL engineers ensure the design meets functional, timing, and power constraints before handing it off for further implementation.

8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976