1

Asic Development Engineer Jobs in Florida (NOW HIRING)

FPGA Engineer

Melbourne, FL · On-site

$120K - $154K/yr

Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation). * Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

FPGA Engineer

Melbourne, FL · On-site

$120K - $154K/yr

Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation). * Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

next page

Showing results 1-20

Asic Development Engineer information

What are popular job titles related to Asic Development Engineer jobs in Florida?

For Asic Development Engineer jobs in Florida, the most frequently searched job titles are:

What job categories do people searching Asic Development Engineer jobs in Florida look for?

The top searched job categories for Asic Development Engineer jobs in Florida are:

What cities in Florida are hiring for Asic Development Engineer jobs?

Cities in Florida with the most Asic Development Engineer job openings:

Infographic showing various Asic Development Engineer job openings in Florida as of July 2026, with employment types broken down into 3% Locum Tenens, 81% Full Time, 5% Part Time, 1% Temporary, 2% Contract, and 8% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution.

$120K - $154K/yr

Full-time

Re-posted 12 days ago


Job description

Required Skills:
  • Expert-level verification engineer with strong SystemVerilog and/ or UVM experience or
  • FPGA verification in lab testing and/or Hardware FPGA design verification testing
  • Experience with design on Xilinx products would be a strong plus
  • expected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities
  • RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
  • Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
  • Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications
  • Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
  • Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.