If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
ASIC & FPGA Design Engineer Sr.
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team ... RTL in VHDL/Verilog/SystemVerilog. Developing synthesis, place and route, and timing closure ...
ASIC & FPGA Design Engineer Sr.
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team ... RTL in VHDL/Verilog/SystemVerilog. Developing synthesis, place and route, and timing closure ...
FPGA Design Engineer
Melbourne, FL · On-site
$114K - $157K/yr
FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Perform RTL coding, simulation, synthesis, place & route, and timing analysis. * Develop FPGA ...
FPGA Design Engineer
Melbourne, FL · On-site
$114K - $157K/yr
FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Perform RTL coding, simulation, synthesis, place & route, and timing analysis. * Develop FPGA ...
ASIC & FPGA Design Engineer Sr.
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team ... RTL in VHDL/Verilog/SystemVerilog. Developing synthesis, place and route, and timing closure ...
ASIC & FPGA Design Engineer Sr.
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team ... RTL in VHDL/Verilog/SystemVerilog. Developing synthesis, place and route, and timing closure ...
Hardware / Electrical Engineer (FPGA)
Melbourne, FL · On-site
$120K - $140K/yr
RTL design & simulation (VHDL, Verilog, SystemVerilog) Develop UVM test environments Perform static ... Strong FPGA/ASIC verification experience (5+ years minimum) Experience with DO-254 documentation ...
Hardware / Electrical Engineer (FPGA)
Melbourne, FL · On-site
$120K - $140K/yr
RTL design & simulation (VHDL, Verilog, SystemVerilog) Develop UVM test environments Perform static ... Strong FPGA/ASIC verification experience (5+ years minimum) Experience with DO-254 documentation ...
ASIC & FPGA Design Engineer Sr
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... Defining FPGA architecture and drafting design specifications; writing clean RTL in VHDL/Verilog ...
ASIC & FPGA Design Engineer Sr
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... Defining FPGA architecture and drafting design specifications; writing clean RTL in VHDL/Verilog ...
ASIC & FPGA Design Engineer Sr
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... Defining FPGA architecture and drafting design specifications; writing clean RTL in VHDL/Verilog ...
ASIC & FPGA Design Engineer Sr
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... Defining FPGA architecture and drafting design specifications; writing clean RTL in VHDL/Verilog ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
ASIC & FPGA Design Engineer Sr
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... RTL in VHDL/Verilog/SystemVerilog that satisfies performance, power, and reliability targets. • ...
ASIC & FPGA Design Engineer Sr
Orlando, FL · On-site
$114K - $158K/yr
You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team ... RTL in VHDL/Verilog/SystemVerilog that satisfies performance, power, and reliability targets. • ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Fpga Design Engineer
$75 - $90/hr
Strong skills in RTL design (VHDL/Verilog/SystemVerilog), timing closure, and block design ... The engineer will collaborate across hardware and software teams, mentor junior engineers, and ...
New
Quick apply
Fpga Design Engineer
$75 - $90/hr
Strong skills in RTL design (VHDL/Verilog/SystemVerilog), timing closure, and block design ... The engineer will collaborate across hardware and software teams, mentor junior engineers, and ...
New
FPGA Engineer/ FPGA Hardware Engineer (level 2 or 3)
Melbourne, FL · On-site
$70K - $100K/hr
Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog. * Develop Hardware ... Perform ASIC/FPGA/SoPC verification using inspection, analysis, simulation, and test methods.
Quick apply
FPGA Engineer/ FPGA Hardware Engineer (level 2 or 3)
Melbourne, FL · On-site
$70K - $100K/hr
Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog. * Develop Hardware ... Perform ASIC/FPGA/SoPC verification using inspection, analysis, simulation, and test methods.
Sr. RTL Engineer
Orlando, FL · On-site
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
Quick apply
Sr. RTL Engineer
Orlando, FL · On-site
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
Sr. RTL Engineer
Orlando, FL · On-site
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of MicroVision ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
Sr. RTL Engineer
Orlando, FL · On-site
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of MicroVision ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of MicroVision ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
MicroVision has an immediate opportunity for a Senior RTL Engineer. As a key member of MicroVision ... Experience with ASIC design & migration from FPGA prototypes to production ASICs Required Education ...
Contractual Asic Rtl Design Engineer information
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
Apple rating
8.0
Based on 674 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
This role will build upon your solid foundation in digital logic circuits while introducing mixed signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits.
Description
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Preferred Qualifications
Proven knowledge of RTL design, Verilog and SystemVerilog
Deep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)
Low power design methodologies and techniques to reduce dynamic and static IC power
ECO design flows and methodologies
Proven understanding of mixed signal concepts and experience with analog circuit behavioral modeling
Proven knowledge of synthesis, static timing and DFT
Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques
Knowledge of scripting languages (i.e. Perl, JSON and Python)
Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code
Digital signal processing fundamentals including signal processing concepts
Strong communication and presentation skills
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976