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Asic Development Engineer Jobs in Melbourne, FL (NOW HIRING)

Sapsol Technologies Inc

FPGA Engineer

Melbourne, FL · On-site

$120K - $154K/yr

Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation). * Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

New

Sapsol Technologies Inc

FPGA Engineer

Melbourne, FL

$120K - $154K/yr

Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation). * Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

New

Apple

Timing Design Engineer

Melbourne, FL

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Apple

Timing Design Engineer

Melbourne, FL · On-site

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Info Way Solutions

Embedded Engineer - FPGA

Melbourne, FL · On-site

$120K - $154K/yr

... Functional Verification of FPGA/ASIC/PLDs * Expertise in Functional Verification, SV/UVM ... Prior experience in DO-254 and Certification of airborne devices, preferably DAL-A developments

New

Apple

Timing Design Engineer

Melbourne, FL

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Apple

Timing Design Engineer

Melbourne, FL · On-site

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

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Showing results 1-20

All JobsAsic Development Engineer JobsAsic Development Engineer Jobs in Melbourne, FL

Asic Development Engineer information

See Melbourne, FL salary details

$45.4K

$89.1K

$142.3K

How much do asic development engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for asic development engineer in Melbourne, FL is $89,128.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,700.00 and $98,700.00 per year, depending on experience, location, and employer.

What engineer makes $500,000 a year?

An experienced ASIC Development Engineer working in high-demand sectors such as semiconductor design or advanced chip development can earn $500,000 or more annually, especially with seniority, specialized skills, and in competitive markets. Compensation often includes base salary, bonuses, and stock options, particularly in large tech or semiconductor companies.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What engineers make $300,000 a year?

Senior engineers in high-demand fields such as software engineering, data engineering, and ASIC development can earn $300,000 or more annually, especially with extensive experience, specialized skills, and working in competitive industries or companies. Roles like senior hardware or ASIC design engineers often reach this level with advanced technical expertise and leadership responsibilities.

Are ASIC engineers in demand?

ASIC development engineers are in high demand due to the growth of industries like consumer electronics, telecommunications, and automotive systems that require custom integrated circuits. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA prototyping and verification, enhance employability in this field.

How much do ASIC engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.
What are popular job titles related to Asic Development Engineer jobs in Melbourne, FL? For Asic Development Engineer jobs in Melbourne, FL, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Melbourne, FL look for? The top searched job categories for Asic Development Engineer jobs in Melbourne, FL are:
Asic Development Engineer jobs near you

FPGA Engineer

Sapsol Technologies Inc

Melbourne, FL • On-site

$120K - $154K/yr

Full-time

Posted 3 days ago

New

Job description

Required Skills:
  • Expert-level verification engineer with strong SystemVerilog and/ or UVM experience or
  • FPGA verification in lab testing and/or Hardware FPGA design verification testing
  • Experience with design on Xilinx products would be a strong plus
  • expected to communicate effectively with emerging engineers at the India GETC-I site and provide both technical and process (DO-254) guidance to the verification team.

Core Responsibilities
  • RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
  • Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
  • Hardware Lifecycle: Handle requirements capture, decomposition, architecture development, synthesis, and placement & routing. [1]

Key Qualifications
  • Experience: Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior designation).
  • Education: Degree in a STEM (Science, Technology, Engineering, Mathematics) field.

Apply