RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Melbourne, FL · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Sr. FPGA Design Engineer - Melbourne, FL / Remote - Fulltime/ Contract Opportunity
Melbourne, FL · Remote
$125K - $173K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
Sr. FPGA Design Engineer - Melbourne, FL / Remote - Fulltime/ Contract Opportunity
Melbourne, FL · Remote
$125K - $173K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Melbourne, FL · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Senior FPGA Design Engineer
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Senior FPGA Design Engineer
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Senior FPGA Design Engineer
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
Quick apply
Senior FPGA Design Engineer
Melbourne, FL · On-site
$145K - $175K/yr
ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Hardware Engineer/ Electrical Engineer (FPGA) - Melbourne, FL - Onsite - Fulltime Opportunity
Melbourne, FL · On-site
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
Hardware Engineer/ Electrical Engineer (FPGA) - Melbourne, FL - Onsite - Fulltime Opportunity
Melbourne, FL · On-site
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
FPGA Engineer
Melbourne, FL · On-site
$120K - $154K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Hardware Engineer/ Electrical Engineer (DO-254) - Permanent / Contract (Both Options are available)
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
Hardware Engineer/ Electrical Engineer (DO-254) - Permanent / Contract (Both Options are available)
Melbourne, FL · On-site
$114K - $151K/yr
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Quick apply
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Core Responsibilities RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog ... Substantial hands-on FPGA or ASIC development experience (typically 5+ years for a senior ...
Freelance Asic Rtl Design Engineer information
See Melbourne, FL salary details
$21.81 is the 25th percentile. Wages below this are outliers.
$13.81 - $23.70
31% of jobs
The median wage is $29.80 / hr.
$23.70 - $33.58
31% of jobs
$33.58 - $43.47
4% of jobs
$52.12 is the 75th percentile. Wages above this are outliers.
$43.47 - $53.35
10% of jobs
$53.35 - $63.24
9% of jobs
$63.24 - $73.12
5% of jobs
$73.12 - $83.01
0% of jobs
$83.01 - $92.89
8% of jobs
$92.89 - $102.78
0% of jobs
$102.78 - $112.66
0% of jobs
$112.66 - $122.55
1% of jobs
$13
$44
$122
How much do freelance asic rtl design engineer jobs pay per hour?
As of Aug 20, 2026, the average hourly pay for freelance asic rtl design engineer in Melbourne, FL is $44.22, according to ZipRecruiter salary data. Most workers in this role earn between $22.50 and $57.26 per hour, depending on experience, location, and employer.
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Melbourne, FL?
For Freelance Asic Rtl Design Engineer jobs in Melbourne, FL, the most frequently searched job titles are:
What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Melbourne, FL look for?
The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Melbourne, FL are:
What cities near Melbourne, FL are hiring for Freelance Asic Rtl Design Engineer jobs?
Cities near Melbourne, FL with the most Freelance Asic Rtl Design Engineer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design career and challenge yourself in a technical and multi-disciplinary endeavor? If so, this is an exciting position in the world class Apple mixed-signal silicon design team!
This role will build upon your solid foundation in digital logic circuits while introducing mixed signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits.
Description
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Proven knowledge of RTL design, Verilog and SystemVerilog
Deep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)
Low power design methodologies and techniques to reduce dynamic and static IC power
ECO design flows and methodologies
Proven understanding of mixed signal concepts and experience with analog circuit behavioral modeling
Proven knowledge of synthesis, static timing and DFT
Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques
Knowledge of scripting languages (i.e. Perl, JSON and Python)
Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code
Digital signal processing fundamentals including signal processing concepts
Strong communication and presentation skills
This role will build upon your solid foundation in digital logic circuits while introducing mixed signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits.
Description
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Proven knowledge of RTL design, Verilog and SystemVerilog
Deep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)
Low power design methodologies and techniques to reduce dynamic and static IC power
ECO design flows and methodologies
Proven understanding of mixed signal concepts and experience with analog circuit behavioral modeling
Proven knowledge of synthesis, static timing and DFT
Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques
Knowledge of scripting languages (i.e. Perl, JSON and Python)
Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code
Digital signal processing fundamentals including signal processing concepts
Strong communication and presentation skills
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976