FPGA Engineer
$118K - $152K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
FPGA Engineer
$118K - $152K/yr
Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
FPGA Engineer
Tampa, FL · On-site
$122K - $157K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
FPGA Engineer
Tampa, FL · On-site
$122K - $157K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
Summary The Senior Custom Logic Engineer demonstrates leadership in technology development and ... Design FPGA, ASIC and CPLD devices for avionics hardware applications, including innovation ...
New
Summary The Senior Custom Logic Engineer demonstrates leadership in technology development and ... Design FPGA, ASIC and CPLD devices for avionics hardware applications, including innovation ...
New
About the Role We are seeking an exceptional Freelance eCommerce UX/UI & Conversion Optimization ... developers and the A/B testing team to turn UX hypotheses into measurable experiments. * Design ...
About the Role We are seeking an exceptional Freelance eCommerce UX/UI & Conversion Optimization ... developers and the A/B testing team to turn UX hypotheses into measurable experiments. * Design ...
Freelance Asic Rtl Design Engineer information
See Lutz, FL salary details
$21.39 is the 25th percentile. Wages below this are outliers.
$13.55 - $23.25
31% of jobs
The median wage is $29.23 / hr.
$23.25 - $32.95
31% of jobs
$32.95 - $42.64
4% of jobs
$51.13 is the 75th percentile. Wages above this are outliers.
$42.64 - $52.34
10% of jobs
$52.34 - $62.04
9% of jobs
$62.04 - $71.74
5% of jobs
$71.74 - $81.43
0% of jobs
$81.43 - $91.13
8% of jobs
$91.13 - $100.83
0% of jobs
$100.83 - $110.53
0% of jobs
$110.53 - $120.22
1% of jobs
$13
$43
$120
How much do freelance asic rtl design engineer jobs pay per hour?
As of Aug 31, 2026, the average hourly pay for freelance asic rtl design engineer in Lutz, FL is $43.38, according to ZipRecruiter salary data. Most workers in this role earn between $22.07 and $56.15 per hour, depending on experience, location, and employer.
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Lutz, FL?
For Freelance Asic Rtl Design Engineer jobs in Lutz, FL, the most frequently searched job titles are:
What cities near Lutz, FL are hiring for Freelance Asic Rtl Design Engineer jobs?
Cities near Lutz, FL with the most Freelance Asic Rtl Design Engineer job openings:
Job description
Apply Now
RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm
Full Time
Travel required to 10%.
Must be able to apply for and maintain a U.S. Government Security Clearance
FPGA Engineer
The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.
Key Responsibilities
FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.
Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.
Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.
Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.
Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.
System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.
Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.
Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.
Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.
About EndoSec
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
11 - 50 Employees
Headquarters location
Washington, DC, US
Year founded
2013