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Asic Physical Design Jobs (NOW HIRING)

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362.50K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site

$175K - $362.50K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

Micron

Engineer, ASIC Physical Design

Minneapolis, MN

$142.51K - $176K/yr

Chip floor-planning, physical design, IP integration, static timing analysis, design validation, and required tape-out revisions. Implement and manage the layout process including floor-planning ...

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Medtronic

Principal ASIC Design Engineer

Moundsview, MN · On-site

ASIC physical design implementation: synthesis, Static Timing Analysis (STA), Place and Route (PAR), UPF/CPF Interact with Place and Route, Static Timing Analysis team to drive best implementation ...

Apple

SoC Physical Design Methodology Engineer

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... ASIC physical design and physical verification checks Scripting skills perl/python/tcl to debug flow related issues and automate checksExperienced in industry standard tools used for physical ...

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Asic Physical Design information

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$95K

$141.5K

How much do asic physical design jobs pay per year?

As of May 31, 2026, the average yearly pay for asic physical design in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Physical Design Engineer, and why are they important?

To thrive as an ASIC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and experience with the ASIC design flow, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL or Perl, are typically required. Strong problem-solving skills, attention to detail, and effective communication enhance collaboration within cross-functional teams. These capabilities ensure the efficient design, optimization, and delivery of high-performance, manufacturable integrated circuits.

What are some common challenges faced by ASIC Physical Design engineers during the tape-out phase, and how can they be addressed?

ASIC Physical Design engineers often encounter challenges such as meeting tight timing closure requirements, resolving signal integrity issues, and managing power consumption during the tape-out phase. These challenges require close collaboration with verification, synthesis, and DFT teams, as well as the use of industry-standard EDA tools for thorough analysis and optimization. Proactive communication, rigorous design reviews, and adopting a structured sign-off checklist can help address potential bottlenecks and ensure a successful tape-out.

What are ASIC Physical Design engineers?

ASIC Physical Design engineers are professionals who take a digital circuit design and transform it into a physical layout that can be manufactured as an integrated circuit (IC) chip. They are responsible for tasks like floorplanning, placement, clock tree synthesis, routing, and ensuring the chip meets timing, power, and area requirements. Their work is critical in bridging the gap between a chip's logical design and its actual fabrication in silicon. ASIC Physical Design engineers use Electronic Design Automation (EDA) tools to optimize and verify the chip design before manufacturing. They play a key role in delivering high-performance, reliable, and cost-effective semiconductors.

What is the difference between Asic Physical Design vs Asic Verification Engineer?

AspectAsic Physical DesignAsic Verification Engineer
Primary FocusImplementing physical layout, placement, routing of ASICsVerifying functionality and performance of ASIC designs
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages, simulation tools, testbench development
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, testing environments, design verification teams
Industry UsageFoundries, semiconductor companies, chip design firmsASIC design companies, semiconductor firms, EDA tool providers

While both roles are integral to ASIC development, Asic Physical Design focuses on the physical implementation of chip layouts, whereas Asic Verification Engineer concentrates on testing and validating the design to ensure it meets specifications.

More about Asic Physical Design jobs
What cities are hiring for Asic Physical Design jobs? Cities with the most Asic Physical Design job openings:
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Asic Physical Design jobs near you
Infographic showing various Asic Physical Design job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $139,408 per year, or $67 per hour.
ASIC Physical Design Principal Consultant

ASIC Physical Design Principal Consultant

Sonsoft Inc

Hillsboro, OR

$148.10K - $152.50K/yr

Full-time

Posted 14 days ago

Job description

Company Description

Sonsoft , Inc. is a USA based corporation duly organized under the laws of the Commonwealth of Georgia. Sonsoft Inc. is growing at a steady pace specializing in the fields of Software Development, Software Consultancy and Information Technology Enabled Services.

Job Description
  • At least 10 years of experience in VLSI/ASIC Design.
  • At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG) on 45nm, 22nm, 14nm, or lower process technology.
  • At least 9 years of experience in Project life cycle activities on development and maintenance projects..
  • At least 8 years of experience in Physical Design and STA review..
  • At least 8 years of experience in ASIC development life cycle..
  • Ability to work in team in diverse/ multiple stakeholder environment.
  • Experience on Intel ASIC flow development.
  • Exposure to DFT is preferred.
  • Analytical and Communication skills.
  • Planning and Co-ordination skills.
  • Experience with project management.
  • Experience and desire to work in a management consulting environment that requires regular travel..
Qualifications
  • Bachelor's degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
  • At least 11 years of experience with Information Technology..
Additional Information

** U.S. citizens and those authorized to work in the U.S. are encouraged to apply. We are unable to sponsor at this time.

Note:-

  1. This is a Full-Time Permanent job opportunity for you.
  2. Only US Citizen, Green Card Holder, TN Visa, GC-EAD, H4-EAD & L2-EAD can apply.
  3. No OPT-EAD & H1B Consultants please.
  4. Please mention your Visa Status in your email or resume.
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About Sonsoft

Sourced by ZipRecruiter

Sonsoft , Inc. is a USA based corporation duly organized under the laws of the Commonwealth of Georgia. Sonsoft Inc. is growing at a steady pace specializing in the fields of Software Development, Software Consultancy and Information Technology Enabled Services.

Industry

It services

Company size

51 - 200 Employees

Headquarters location

Alpharetta, GA, US

Year founded

2007

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