... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL ... full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and ...
ASIC Design Engineer
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
ASIC Design Engineer
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
ASIC / VLSI Engineers
Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
ASIC / VLSI Engineers
Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
PRINCIPAL RTL DESIGN
Boise, ID · On-site
$129K - $133K/yr
Overview Micron Technology seeks a Principal RTL Design Engineer to lead the development of ... Strong experience with ASIC low‐power design methodologies, including UPF‐based power intent ...
PRINCIPAL RTL DESIGN
Boise, ID · On-site
$129K - $133K/yr
Overview Micron Technology seeks a Principal RTL Design Engineer to lead the development of ... Strong experience with ASIC low‐power design methodologies, including UPF‐based power intent ...
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
Full Time Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do full time asic rtl design engineer jobs pay per year?
As of Aug 21, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What is a full time ASIC RTL design engineer?
Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.
What are some common challenges full time ASIC RTL design engineers face when collaborating with verification teams?
A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.
What are the key skills and qualifications needed to thrive as a full time ASIC RTL design engineer, and why are they important?
To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.
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Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Do you love creating sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you'll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 3 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 3 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976