Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Design Engineer
San Jose, CA · On-site
Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
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Design Engineer
San Jose, CA · On-site
Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159.60K/yr
... in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development ... The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits.
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159.60K/yr
... in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development ... The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits.
RTL Design Engineer
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
RTL Design Engineer
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
... ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. * Design ... The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits.
... ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. * Design ... The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits.
RTL Design Engineer
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
RTL Design Engineer
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... years of full time ASIC design experiencememory system developmentRTL/micro-architecture ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... years of full time ASIC design experiencememory system developmentRTL/micro-architecture ...
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits.
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... Work with physical design team on the timing closure of the cache subsystem. 3+ years of full time ...
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem ... Work with physical design team on the timing closure of the cache subsystem. 3+ years of full time ...
ASIC Digital Design, Sr Staff Engineer - 15247
Austin, TX · On-site
$138K/yr
Define and develop ASIC RTL design and verification at both chip level and block level ... Conduct design reviews and provide technical guidance to junior engineers. * Work closely with ...
ASIC Digital Design, Sr Staff Engineer - 15247
Austin, TX · On-site
$138K/yr
Define and develop ASIC RTL design and verification at both chip level and block level ... Conduct design reviews and provide technical guidance to junior engineers. * Work closely with ...
ASIC Digital Design, Architect - 15036
Austin, TX · On-site
$181K - $271K/yr
... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...
ASIC Digital Design, Architect - 15036
Austin, TX · On-site
$181K - $271K/yr
... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...
16218 - ASIC Digital Design, Sr Manager
Sunnyvale, CA · On-site
$204K - $306K/yr
General Information Job Title ASIC Digital Design, Sr Manager Job ID 16218 City Sunnyvale State ... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ...
16218 - ASIC Digital Design, Sr Manager
Sunnyvale, CA · On-site
$204K - $306K/yr
General Information Job Title ASIC Digital Design, Sr Manager Job ID 16218 City Sunnyvale State ... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ...
The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
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The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development ... Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation ...
As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development ... Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation ...
Must be in San Diego full time, 5 days a week Applicants selected will be subject to a government ... Experience: 10+ years of ASIC design experience * RTL Expertise: System Verilog Design, Linting ...
Must be in San Diego full time, 5 days a week Applicants selected will be subject to a government ... Experience: 10+ years of ASIC design experience * RTL Expertise: System Verilog Design, Linting ...
The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ... UNAVAILABLEEmployment Type: FULL_TIME
The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ... UNAVAILABLEEmployment Type: FULL_TIME
Full Time Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do full time asic rtl design engineer jobs pay per year?
As of May 30, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a Full Time ASIC RTL Design Engineer, and why are they important?
To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.
What are some common challenges Full Time ASIC RTL Design Engineers face when collaborating with verification teams?
A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.
What are Full Time ASIC RTL Design Engineers?
Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.
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Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Apple’s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple’s products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Preferred Qualifications
Experience: 8+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Preferred Qualifications
Experience: 8+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976