Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
Minimum Qualifications 10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background ...
ASIC / VLSI Engineers
Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
ASIC / VLSI Engineers
Milpitas, CA · On-site
... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
Minimum Qualifications 3+ years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis B.S. in a relevant field ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC Digital Design, Sr. Staff Engineer-17369
Boxborough, MA · On-site
$138K/yr
Running RTL and gate-level simulations. * Supporting application engineers and customers on HBM/DDR ... ASIC RTL design and verification experience. * Verilog, PERL, TCL, Python skills. * Static timing ...
ASIC Digital Design, Sr. Staff Engineer-17369
Boxborough, MA · On-site
$138K/yr
Running RTL and gate-level simulations. * Supporting application engineers and customers on HBM/DDR ... ASIC RTL design and verification experience. * Verilog, PERL, TCL, Python skills. * Static timing ...
The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ... UNAVAILABLEEmployment Type: FULL_TIME
The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ... UNAVAILABLEEmployment Type: FULL_TIME
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to ... Minimum 10+ years of ASIC RTL design and/or architecture experience * Proven track record with the ...
We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to ... Minimum 10+ years of ASIC RTL design and/or architecture experience * Proven track record with the ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Full Time Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do full time asic rtl design engineer jobs pay per year?
As of Jul 11, 2026, the average yearly pay for full time asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What are Full Time ASIC RTL Design Engineers?
Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.
What are the key skills and qualifications needed to thrive as a Full Time ASIC RTL Design Engineer, and why are they important?
To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.
What are some common challenges Full Time ASIC RTL Design Engineers face when collaborating with verification teams?
A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.
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What are the most commonly searched types of Asic Rtl Design Engineer jobs? The most popular types of Asic Rtl Design Engineer jobs are:
What states have the most Full Time Asic Rtl Design Engineer jobs? States with the most job openings for Full Time Asic Rtl Design Engineer jobs include:
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Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Apple is building the world's fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
10 + years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
Cache design background including an understanding of different memory organizations and tradeoffs.
Hands on Experience with multi-processor cache coherence protocols
B.S. in a relevant field
Preferred Qualifications
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.
Description
Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.
Minimum Qualifications
10 + years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
Cache design background including an understanding of different memory organizations and tradeoffs.
Hands on Experience with multi-processor cache coherence protocols
B.S. in a relevant field
Preferred Qualifications
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976