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Freelance Asic Rtl Design Engineer Jobs (NOW HIRING)

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

SR RTL DESIGN

Boise, ID · On-site

$100 - $125/hr

Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

ASIC Design Engineer

San Diego, CA · On-site

$100 - $125/hr

Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

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Freelance Asic Rtl Design Engineer information

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How much do freelance asic rtl design engineer jobs pay per hour?

As of Sep 9, 2026, the average hourly pay for freelance asic rtl design engineer in the United States is $47.71, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $61.78 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
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Infographic showing various Freelance Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 65% Full Time, and 35% Contract. Highlights an 85% In-person, and 15% Remote job distribution, with an average salary of $99,230 per year, or $47.7 per hour.

ASIC RTL/SoC Design Engineer

Fremont, CA

TetraMem INC
Computer and Peripheral Equipment Manufacturing • 11 - 50 employees

Full-time

Medical, Retirement, PTO

Re-posted 3 days ago


Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description
  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.

  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.

  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.

  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.

  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.

  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.

  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.

  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.

  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.

  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.

Qualifications
  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

  • Experience with Verilog and system Verilog

  • Experience with VCS, Verdi or other industry standard tools

  • Experience with pre-layout simulation and post-layout simulation

  • Understanding of the design flow. Ability to work with the backend team

  • Familiarity with AMBA APB AXI Protocol

  • Familiarity with RISC/Arm or other core architectures

  • Ability to create innovative architecture and solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems

  • Working knowledge of SoC architecture such as CPU, GPU or accelerators

  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Additional Information

All your information will be kept confidential according to EEO guidelines.