RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
San Jose, CA · On-site
Medical
Dental
Vision
Life
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
New
San Jose, CA · On-site
Medical
Dental
Vision
Life
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
New
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Boise, ID · On-site
$110 - $170/hr
Medical
Dental
Vision
PTO
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Boise, ID · On-site
$110 - $170/hr
Medical
Dental
Vision
PTO
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Boise, ID · On-site
$100 - $130/hr
Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...
Boise, ID · On-site
$100 - $130/hr
Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Austin, TX · On-site +1
Medical
Dental
Vision
Life
Retirement
PTO
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Austin, TX · On-site +1
Medical
Dental
Vision
Life
Retirement
PTO
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
San Diego, CA · On-site
$99 - $148/hr
Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...
San Diego, CA · On-site
$99 - $148/hr
Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
Boise, ID · On-site
$120 - $180/hr
Medical
Dental
Vision
PTO
The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...
Boise, ID · On-site
$120 - $180/hr
Medical
Dental
Vision
PTO
The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
$23.52 is the 25th percentile. Wages below this are outliers.
$14.90 - $25.57
31% of jobs
The median wage is $32.14 / hr.
$25.57 - $36.23
31% of jobs
$36.23 - $46.90
4% of jobs
$56.23 is the 75th percentile. Wages above this are outliers.
$46.90 - $57.56
10% of jobs
$57.56 - $68.23
9% of jobs
$68.23 - $78.89
5% of jobs
$78.89 - $89.55
0% of jobs
$89.55 - $100.22
8% of jobs
$100.22 - $110.88
0% of jobs
$110.88 - $121.55
0% of jobs
$121.55 - $132.21
1% of jobs
$14
$47
$132
Cities with the most Freelance Asic Rtl Design Engineer job openings:
The most popular types of Asic Rtl Design Engineer jobs are:
States with the most job openings for Freelance Asic Rtl Design Engineer jobs include:
The top searched job categories for Freelance Asic Rtl Design Engineer jobs are:

RTL Design Engineer
Building AI chips that are hard-coded for individual model architectures.
RTL Design Engineer
As an RTL Engineer, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.
In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of the team's success.
Representative projects:
You may be a good fit if you:
Strong candidates may also have experience with:
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1 - 10 Employees
Mission Hills, CA, US
2013