1

Freelance Asic Rtl Design Engineer Jobs (NOW HIRING)

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

ASIC Digital Design, Sr Manager

Sunnyvale, CA · On-site +1

$204K - $306K/yr

... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...

Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...

RTL Design Engineer

Boise, ID · On-site

$129.40K/yr

Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

RTL Design Engineer

Boise, ID · On-site

$129.40K/yr

Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159.60K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...

... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...

next page

Showing results 1-20

Freelance Asic Rtl Design Engineer information

See salary details

$14

$47

$132

How much do freelance asic rtl design engineer jobs pay per hour?

As of May 30, 2026, the average hourly pay for freelance asic rtl design engineer in the United States is $47.71, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $61.78 per hour, depending on experience, location, and employer.
More about Freelance Asic Rtl Design Engineer jobs
What cities are hiring for Freelance Asic Rtl Design Engineer jobs? Cities with the most Freelance Asic Rtl Design Engineer job openings:
What are the most commonly searched types of Asic Rtl Design Engineer jobs? The most popular types of Asic Rtl Design Engineer jobs are:
What states have the most Freelance Asic Rtl Design Engineer jobs? States with the most job openings for Freelance Asic Rtl Design Engineer jobs include:
What job categories do people searching Freelance Asic Rtl Design Engineer jobs look for? The top searched job categories for Freelance Asic Rtl Design Engineer jobs are:
Infographic showing various Freelance Asic Rtl Design Engineer job openings in the United States as of May 2026, with employment types broken down into 10% Full Time, 40% Part Time, and 50% Contract. Highlights an 87% Physical, 2% Hybrid, and 11% Remote job distribution, with an average salary of $99,230 per year, or $47.7 per hour.
ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

TetraMem INC

Fremont, CA • On-site

Full-time

Medical, Retirement, PTO

Posted 21 days ago


Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description
  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.

  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.

  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.

  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.

  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.

  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.

  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.

  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.

  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.

  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.

Qualifications
  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design

  • Experience with Verilog and system Verilog

  • Experience with VCS, Verdi or other industry standard tools

  • Experience with pre-layout simulation and post-layout simulation

  • Understanding of the design flow. Ability to work with the backend team

  • Familiarity with AMBA APB AXI Protocol

  • Familiarity with RISC/Arm or other core architectures

  • Ability to create innovative architecture and solutions to customer requirements

  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.

Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems

  • Working knowledge of SoC architecture such as CPU, GPU or accelerators

  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Additional Information

All your information will be kept confidential according to EEO guidelines.