... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
ASIC Design Engineer
Austin, TX · On-site
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
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ASIC Design Engineer
Austin, TX · On-site
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
New
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Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
New
ASIC Design Engineer
Richardson, TX · On-site
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Quick apply
ASIC Design Engineer
Richardson, TX · On-site
$80 - $110/hr
ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
SOC Design Engineer
San Jose, CA · On-site
SOC Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
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SOC Design Engineer
San Jose, CA · On-site
SOC Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
Power Engineer (RTL Design)
Austin, TX · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. Strong background in RTL design and verification principles. Demonstrable experience with power profiling tools such as PPRTL or ...
Power Engineer (RTL Design)
Austin, TX · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. Strong background in RTL design and verification principles. Demonstrable experience with power profiling tools such as PPRTL or ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Staff ASIC Design Engineer
Saint Paul, MN · On-site
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
Staff ASIC Design Engineer
Saint Paul, MN · On-site
$140K - $170K/yr
Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Freelance Asic Rtl Design Engineer information
See salary details
$23.52 is the 25th percentile. Wages below this are outliers.
$14.90 - $25.57
31% of jobs
The median wage is $32.14 / hr.
$25.57 - $36.23
31% of jobs
$36.23 - $46.90
4% of jobs
$56.23 is the 75th percentile. Wages above this are outliers.
$46.90 - $57.56
10% of jobs
$57.56 - $68.23
9% of jobs
$68.23 - $78.89
5% of jobs
$78.89 - $89.55
0% of jobs
$89.55 - $100.22
8% of jobs
$100.22 - $110.88
0% of jobs
$110.88 - $121.55
0% of jobs
$121.55 - $132.21
1% of jobs
$14
$47
$132
How much do freelance asic rtl design engineer jobs pay per hour?

Apple rating
8.1
Based on 667 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 0 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976