SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from ...
SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from ...
RTL Design Engineer
Waltham, MA · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Waltham, MA · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Waltham, MA · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
Waltham, MA · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
$116K - $203K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
$116K - $203K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
Senior Staff RTL Design Engineer- 16908
Boxborough, MA · On-site
$120 - $160/hr
You Are You bring extensive ASIC digital design experience with a track record of delivering ... Computer Engineering, or related field * 10+ years of ASIC digital design experience with RTL ...
Senior Staff RTL Design Engineer- 16908
Boxborough, MA · On-site
$120 - $160/hr
You Are You bring extensive ASIC digital design experience with a track record of delivering ... Computer Engineering, or related field * 10+ years of ASIC digital design experience with RTL ...
RTL Design Engineer
$165K - $292K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
RTL Design Engineer
$165K - $292K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design ...
ASIC Digital Design, Sr Staff Engineer - 16908
Boxborough, MA · On-site
$138K/yr
General Information Job Title Senior Staff RTL Design Engineer- 16908 Job ID 16908 City Boxborough State/Province Massachusetts Date Posted 08-Apr-2026 Job Category Engineering Job Subcategory ASIC ...
ASIC Digital Design, Sr Staff Engineer - 16908
Boxborough, MA · On-site
$138K/yr
General Information Job Title Senior Staff RTL Design Engineer- 16908 Job ID 16908 City Boxborough State/Province Massachusetts Date Posted 08-Apr-2026 Job Category Engineering Job Subcategory ASIC ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$134K - $201K/yr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$134K - $201K/yr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$134K - $201K/yr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$134K - $201K/yr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$135 - $202/hr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
Staff Engineer, Digital Design Engineering
Chelmsford, MA · On-site
$135 - $202/hr
About the Role ADI's Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading ... Implement in RTL and debug while collaborating with the verification team to ensure that the design ...
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading ... Implement in RTL and debug while collaborating with the verification team to ensure that the design ...
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading ... Implement in RTL and debug while collaborating with the verification team to ensure that the design ...
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading ... Implement in RTL and debug while collaborating with the verification team to ensure that the design ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
RTL Design Engineer (TERADYNE, North Reading, MA)
North Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is ... Developing specifications, micro-architecture, and RTL design of mission critical blocks in ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
ASIC Design Engineer
Boston, MA · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
ASIC Design Engineer
Boston, MA · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... Own the end-to-end process from RTL delivery through synthesis, power analysis, and timing closure ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... Own the end-to-end process from RTL delivery through synthesis, power analysis, and timing closure ...
Server CPU Physical Design Engineer, Senior/Staff level - Cambridge, UK
Cambridge, MA · On-site
$120.27 - $173.73/hr
Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve ... Physical design experience on CPU cores , high-performance compute blocks, or timing-critical ASIC ...
Server CPU Physical Design Engineer, Senior/Staff level - Cambridge, UK
Cambridge, MA · On-site
$120.27 - $173.73/hr
Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post-silicon teams to improve ... Physical design experience on CPU cores , high-performance compute blocks, or timing-critical ASIC ...
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Other
Posted 8 days ago
Job description
12 Months + CONTRACT Starting in September
SKILLS:
SENIOR ASIC RTL Design
Verilog
High Speed Memory Interface Experience
Logic synthesis & Timing constraints
Forward Error Correction (FEC), Bit Rate Error (BER) calculations
Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation
Prefer experience with some of:
- LPDDR5
- UFS/Flash
- PCIe Gen4/5
About Carlton National Resources
Sourced by ZipRecruiter
Industry
Recruiting and staffing services
Company size
51 - 200 Employees
Headquarters location
Marblehead, MA, US
Year founded
2009