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Freelance Asic Rtl Design Engineer Jobs in Pittsburgh, PA

EndoSec LLC

FPGA Engineer

Pittsburgh, PA

$126K - $162K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

EndoSec LLC

FPGA Engineer

Pittsburgh, PA · On-site

$126K - $162K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

HELLBENDER Inc.

Marketing Specialist

Pittsburgh, PA · Hybrid

$65K - $80K/yr

Support go-to-market activities for Hellbender products by collaborating with product, engineering ... Coordinate with external agencies, freelancers and internal stakeholders to keep campaigns on brand ...

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Freelance Asic Rtl Design Engineer information

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$14

$46

$128

How much do freelance asic rtl design engineer jobs pay per hour?

As of Aug 10, 2026, the average hourly pay for freelance asic rtl design engineer in Pittsburgh, PA is $46.31, according to ZipRecruiter salary data. Most workers in this role earn between $23.56 and $59.95 per hour, depending on experience, location, and employer.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this competitive field.
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Freelance Asic Rtl Design Engineer jobs near you
Infographic showing various Freelance Asic Rtl Design Engineer job openings in Pittsburgh, PA as of August 2026, with employment types broken down into 100% Full Time. Highlights an 67% In-person, and 33% Hybrid job distribution, with an average salary of $96,334 per year, or $46.3 per hour.

FPGA Engineer

EndoSec LLC

Pittsburgh, PA

$126K - $162K/yr

Full-time

Re-posted 3 days ago

Job description

Apply Now

RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System Integration, Hardware Security, Xilinx, Simulation, IP core, Versal, Stratix, concept to deployment, Vivado, GHDL, Questa, Quartus Prime, Zynq, Agilex, AXI, ACE, Avalon, FPGA verification tools, reverse engineering, cocotb, pyuvm

Full Time

Travel required to 10%.

Must be able to apply for and maintain a U.S. Government Security Clearance

FPGA Engineer

The EndoSec FPGA Engineer is responsible for the design, development, testing, and maintenance of IP cores and FPGA-based systems used in hardware security applications.

Key Responsibilities

FPGA Design and Development: Design and develop IP cores and FPGA configurations implementing the latest in leakage-resilient hardware cryptography algorithms using state-of-the-art FPGA hardware.

Modeling and Simulation: Use simulation tools and verification frameworks to ensure mathematically-correct logic before hardware deployment.

Hardware/Software Design: Work closely with other engineers to integrate FPGA designs with application software and embedded systems. Implement embedded software-based testing solutions where applicable to validate FPGA designs.

Performance Optimization: Optimize FPGA designs for timing, resource utilization, and throughput. Identify and resolve system bottlenecks.

Testing and Validation: Create comprehensive test and verification plans for FPGA components, conduct unit and integration testing, and validate hardware performance against requirements in a remote environment.

System Integration: Ensure seamless integration between internally-developed and third-party IP cores, FPGA designs, and embedded systems. Collaborate with other engineers to develop and maintain system-level architecture.

Troubleshooting and Debugging: Utilize debugging tools and techniques to diagnose and resolve issues within FPGA designs and hardware platforms.

Documentation: Prepare detailed documentation, including design specifications, testing protocols, and user guides, to support system development and maintenance.

Continuous Learning: Actively stay up-to-date with the latest advancements in FPGA technology and hardware security to continually refine and enhance system capabilities.

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About EndoSec

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Washington, DC, US

Year founded

2013

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