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Freelance Asic Rtl Design Engineer Jobs in Kansas

FPGA Design Engineer

Lenexa, KS · On-site

$112K - $154K/yr

Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...

FPGA Design Engineer

Lenexa, KS · On-site

$112K - $154K/yr

Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...

FPGA Design Engineer

Lenexa, KS · On-site

$112K - $154K/yr

Develop RTL and support simulation, synthesis, place and route, timing closure, hardware ... Computer Engineering, or a related technical field. * 8+ years of professional FPGA design and ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

RTL/VHDL experience is a plus. * Experience with high-speed interfaces such as SPI, I2C, CAN, USB ... Familiarity with power design and embedded system integration. * Power electronics, motor control ...

... design, copy, motion, and video - including a mix of FTEs and agency/freelance relationships ... Engineering Mindset * A systems thinker who also sweats the details - you can zoom out to brand ...

... of chip design, including artificial intelligence, machine learning, automotive, data center ... Experience working with CPU architects and RTL engineers * Experience developing and debugging ...

... of chip design, including artificial intelligence, machine learning, automotive, data center ... Experience working with CPU and RTL engineers and architects * Experience working with standards ...

... of chip design, including artificial intelligence, machine learning, automotive, data center ... Experience working with hardware RTL engineers * Experience working with standards groups Pay ...

... Developers, User Experience Designers, Interactive Art Directors, SEO Specialists, Quality ... This includes website design and development projects, ongoing website support and improvement, and ...

Freelance Asic Rtl Design Engineer information

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this competitive field.
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FPGA Design Engineer

GuideTech LLC

Lenexa, KS • On-site

$112K - $154K/yr

Full-time

Re-posted 11 days ago


Job description

Job Type
Full-time
Description
Location: Lenexa, KS
GuideTech, a subsidiary of Palladyne AI (NASDAQ: PDYN), builds high-performance avionics and autonomy software for aerospace, space, and defense systems. We support a wide array of vehicles, from small multi-rotors and heavy lift UAVs to unmanned fighter jets, launch vehicles, spacecraft, re-entry vehicles, missiles, and counter-UAS interceptors. Our culture is grounded in trust, integrity, and a shared commitment to meaningful work.
Position Summary
We're seeking an experienced FPGA Design Engineer to develop FPGA solutions for next-generation avionics systems. In this role, you'll work on mission-critical aerospace and defense technologies, collaborating with hardware, software, systems, and test engineering teams to bring FPGA designs from concept through hardware validation.
What You'll Do
  • Design and implement FPGA solutions using VHDL.
  • Develop RTL and support simulation, synthesis, place and route, timing closure, hardware verification, and implementation.
  • Collaborate with cross-functional engineering teams to integrate FPGA designs into avionics hardware.
  • Support board bring-up, debugging, and hardware validation.
  • Participate in design reviews and technical documentation.

Requirements
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 8+ years of professional FPGA design and development experience.
  • Strong RTL design experience using VHDL.
  • Experience with the complete FPGA development lifecycle, including RTL design, simulation, synthesis, place and route, timing closure, implementation, and hardware verification.
  • Experience developing FPGA solutions using AMD/Xilinx devices and the Vivado tool suite.
  • Strong understanding of digital logic design, hardware architecture, and hardware/software interaction.
  • Ability to read and understand electrical schematics.
  • Experience using laboratory equipment, including oscilloscopes, spectrum analyzers, signal sources, and power supplies.
  • Strong verbal and written communication skills with the ability to collaborate across multidisciplinary engineering teams.
  • Experience with Git, ModelSim/QuestaSim, and scripting languages such as Python, Perl, or Ruby.

Work Authorization & Clearance
This position requires the ability to work in the United States without current or future sponsorship.
Depending on the nature of the work, the ability to obtain and maintain a U.S. security clearance may be required. Candidates may be asked to provide additional information relevant to clearance eligibility in accordance with applicable laws and regulations.
Work Environment
This role is based onsite in Lenexa, KS and may involve working in both an office and light production environment. Responsibilities may include occasional standing, lifting, and handling of equipment or materials.
The Fine Print
No 3rd party candidates will be accepted
It is Palladyne AI's policy to provide equal employment opportunity (EEO) to all persons regardless of race, color, religion, sex, national origin, age, sexual orientation, gender identity, genetic information, physical or mental disability, protected veteran status, or any other characteristic protected by federal, state/provincial, local law.