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Asic Rtl Design Engineer Jobs (NOW HIRING)

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Engineering, or a related field.Experience: 3+ years of proven experience in ASIC design, including ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ...

Synopsys

ASIC Digital Design, Sr Manager

Sunnyvale, CA · On-site +1

$204K - $306K/yr

... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

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How much do asic rtl design engineer jobs pay per year?

As of Jun 18, 2026, the average yearly pay for asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC RTL Design Engineer job?

An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.

What are the typical daily responsibilities of an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.

What are the key skills and qualifications needed to thrive in the Asic Rtl Design Engineer position, and why are they important?

To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

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Infographic showing various Asic Rtl Design Engineer job openings in the United States as of June 2026, with employment types broken down into 79% Full Time, 18% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

TetraMem - Accelerate The World

San Jose, CA

$110K - $300K/yr

Other

Posted 8 days ago

Job description

Responsibilities:

  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications
  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery


Requirements:

  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
  • Experience with Verilog and system Verilog
  • Experience with VCS, Verdi or other industry standard tools
  • Experience with pre-layout simulation and post-layout simulation
  • Understanding of the design flow. Ability to work with the backend team
  • Familiarity with AMBA APB AXI Protocol
  • Familiarity with RISC/Arm or other core architectures
  • Ability to create innovative architecture and solutions to customer requirements
  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.


Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems
  • Working knowledge of SoC architecture such as CPU, GPU or accelerators
  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Salary Range: $110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.
TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.
To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMems official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.
We encourage all interested candidates to apply through the official TetraMem Careers page.

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