RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA · On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
New
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
New
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Sr Digital Design Engineer
Boise, ID · On-site
$110 - $170/hr
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Sr Digital Design Engineer
Boise, ID · On-site
$110 - $170/hr
Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
SR RTL DESIGN
Boise, ID · On-site
$100 - $130/hr
Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...
SR RTL DESIGN
Boise, ID · On-site
$100 - $130/hr
Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
ASIC Design Engineer
San Diego, CA · On-site
$99 - $148/hr
Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...
ASIC Design Engineer
San Diego, CA · On-site
$99 - $148/hr
Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...
ASIC Design Engineer
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
ASIC Design Engineer
San Diego, CA · On-site
Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...
SrvDigital Design Engineer
Boise, ID · On-site
$120 - $180/hr
The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...
SrvDigital Design Engineer
Boise, ID · On-site
$120 - $180/hr
The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Asic Rtl Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do asic rtl design engineer jobs pay per year?
As of Aug 20, 2026, the average yearly pay for asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What is an ASIC RTL design engineer?
An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.
What are the typical daily responsibilities of an ASIC RTL design engineer?
As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.
What are the key skills and qualifications needed to thrive in the ASIC RTL design engineer position, and why are they important?
To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.
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Job description
RTL Design Engineer
Building AI chips that are hard-coded for individual model architectures.
RTL Design Engineer
As an RTL Engineer, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.
In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of the team's success.
Representative projects:
- Implement a block to efficiently compute floating point math operators
- Provide feedback to the uArch team to make sure blocks meet timing and area constraints
You may be a good fit if you:
- At least 5 years of work experience in RTL development.
- Experience with high-speed digital logic.
- Proficiency in standard RTL design and synthesis tools
- Familiarity with verification work and writing test benches
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
- Willing to start quickly
Strong candidates may also have experience with:
- Experience with PCIe, Ethernet, or HBM technologies
- Familiarity with transformer models and machine learning.
- Familiarity with numerical representations and functions
- Ability to program with Python or another scripting language
About Ethan Alexander Group
Sourced by ZipRecruiter
Industry
Recruiting and staffing services
Company size
1 - 10 Employees
Headquarters location
Mission Hills, CA, US
Year founded
2013