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Asic Rtl Design Engineer Jobs in Philadelphia, PA

ASIC/FPGA Design Engineer (SMES) Job Code: 34234 Job Location: Camden, NJ Schedule: 9/80 Regular ... Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate ...

FPGA/ASIC Design Engineer

Camden, NJ · On-site

$124K - $171K/yr

Job #215247 Chipton-Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ. BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE) At least 3 year experience with proven ...

FPGA Engineer

Exton, PA · On-site

$125K - $161K/yr

Bachelor's degree in Electrical Engineering or equivalent experience * 2+ years of FPGA or ASIC ... Solid understanding of FPGA development workflows including RTL design, verification, logic ...

FPGA Engineer

Exton, PA

$125K - $161K/yr

Bachelor's degree in Electrical Engineering or equivalent experience * 2+ years of FPGA or ASIC ... Solid understanding of FPGA development workflows including RTL design, verification, logic ...

FPGA Engineer

Exton, PA · On-site

$125K - $161K/yr

Bachelor's degree in Electrical Engineering or equivalent experience * 2+ years of FPGA or ASIC ... Solid understanding of FPGA development workflows including RTL design, verification, logic ...

FPGA Engineer

Moorestown, NJ

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

FPGA Engineer

Moorestown, NJ · On-site

$128K - $164K/yr

Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Establishes design concepts, criteria and engineering efforts for product research, development ... ASIC Engineering development, system and product qualification and NSA certification, low-rate ...

Asic Rtl Design Engineer information

See Philadelphia, PA salary details

$94.9K

$151.6K

$203.8K

How much do asic rtl design engineer jobs pay per year?

As of Jun 11, 2026, the average yearly pay for asic rtl design engineer in Philadelphia, PA is $151,560.00, according to ZipRecruiter salary data. Most workers in this role earn between $132,700.00 and $181,600.00 per year, depending on experience, location, and employer.

What is an ASIC RTL Design Engineer job?

An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.

What are the typical daily responsibilities of an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.

What are the key skills and qualifications needed to thrive in the Asic Rtl Design Engineer position, and why are they important?

To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Philadelphia, PA? The most popular types of Asic Rtl Design Engineer jobs in Philadelphia, PA are:
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Infographic showing various Asic Rtl Design Engineer job openings in Philadelphia, PA as of June 2026, with employment types broken down into 79% Full Time, 18% Part Time, and 3% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $151,560 per year, or $72.9 per hour.

ASIC/FPGA Design Engineer IV with Security Clearance

Global Edge Group, LLC

King Of Prussia, PA

$124K - $220K/yr

Other

Posted 22 days ago


Job description

The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need. Job Title: ASIC/FPGA Design Engineer IV – TS/SCI Clearance
Location: Boulder, CO; King of Prussia, PA; Littleton, CO; Louisville, CO; Sunnyvale, CA
Type of Role: Direct Hire (Full-Time, Onsite)
Shift: 9x80 Schedule (Every other Friday off)
Pay: Approximately $124,800 – $220,000/year POSITION OVERVIEW:
We are seeking an experienced ASIC/FPGA Design Engineer IV to support advanced space and national security programs within a highly classified aerospace and defense environment. This role is responsible for supporting FPGA and ASIC design, development, integration, and verification efforts for mission-critical space systems and secure hardware architectures. The ideal candidate has strong experience with FPGA/ASIC development methodologies, HDL programming, hardware integration, and cross-functional engineering collaboration supporting highly complex aerospace and defense initiatives. RESPONSIBILITIES AND ESSENTIAL DUTIES:
• Support FPGA and ASIC design, development, integration, and verification activities for advanced aerospace and defense systems
• Develop and implement FPGA/ASIC architectures supporting mission-critical space and national security applications
• Perform RTL design and development utilizing VHDL, Verilog, and/or SystemVerilog
• Support hardware integration, simulation, testing, debugging, and validation efforts
• Collaborate closely with systems engineering, hardware engineering, software engineering, and verification teams
• Support full FPGA/ASIC lifecycle execution including requirements, architecture, design, implementation, integration, and test
• Participate in design reviews, technical assessments, and engineering documentation activities
• Support timing analysis, synthesis, and hardware optimization efforts
• Utilize FPGA/ASIC development toolchains and simulation environments supporting complex hardware systems
• Support troubleshooting and root-cause analysis for hardware and system integration issues
• Participate in Agile and cross-functional engineering execution environments
• Support mission-critical national security and space system development efforts within highly classified environments MINIMUM REQUIREMENTS:
Basic Qualifications
• Experience with FPGA and/or ASIC design and development methodologies
• Experience programming utilizing VHDL, Verilog, and/or SystemVerilog
• Experience supporting hardware integration, simulation, and testing activities
• Familiarity with FPGA/ASIC toolchains and hardware development environments
• Ability to collaborate effectively within cross-functional engineering teams
• Active Top Secret Clearance required
• Ability to obtain and maintain TS/SCI eligibility
• U.S. Citizenship required Additional Qualifications
• Experience with FPGA synthesis, timing analysis, and hardware optimization
• Experience supporting mission-critical aerospace, defense, or national security systems
• Familiarity with ASIC verification and validation methodologies
• Experience with embedded hardware systems and high-reliability architectures preferred
• Strong troubleshooting and hardware debugging capabilities
• Experience supporting Agile engineering and collaborative development environments
• Excellent communication and technical documentation skills
• Experience supporting highly classified space or defense programs preferred The Global Edge Consultants, LLC is an Equal Opportunity Employer. The Global Edge Consultants, LLC does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.