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Asic Rtl Design Engineer Jobs (NOW HIRING)

Google

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...

Etched

RTL Design Engineer

Cupertino, CA

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$129K - $194K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$129K - $194K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...

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Asic Rtl Design Engineer information

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How much do asic rtl design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is an ASIC RTL design engineer?

An ASIC RTL Design Engineer is responsible for designing and implementing the digital logic of Application-Specific Integrated Circuits (ASICs) using Hardware Description Languages (HDLs) like Verilog or VHDL. They translate system-level specifications into Register Transfer Level (RTL) code, ensuring functionality, performance, and power efficiency. Their role also involves simulation, synthesis, timing analysis, and debugging to verify and optimize the design. They collaborate with verification, physical design, and firmware teams to ensure seamless integration.

What are the typical daily responsibilities of an ASIC RTL design engineer?

As an ASIC RTL Design Engineer, your daily responsibilities often include designing and verifying Register Transfer Level (RTL) code for specific chip modules, running simulations, and debugging functional issues. You will frequently collaborate with verification engineers, physical design teams, and system architects to ensure the design meets specifications and performance goals. The role also involves attending regular team meetings to coordinate project tasks and document progress. Staying current with evolving industry methodologies and engaging in code reviews are also part of the typical workflow.

What are the key skills and qualifications needed to thrive in the ASIC RTL design engineer position, and why are they important?

To thrive as an ASIC RTL Design Engineer, you need a strong background in digital logic design, Verilog or VHDL coding, and a relevant degree in electrical or computer engineering. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, and ModelSim, as well as familiarity with simulation and synthesis processes, is typically required. Attention to detail, strong problem-solving abilities, and effective communication skills are highly valued in this position. These competencies are essential to ensuring robust, efficient, and collaborative chip development within project timelines.

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Asic Rtl Design Engineer jobs near you
Infographic showing various Asic Rtl Design Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Staff ASIC Design Engineer

ForwardEdge ASIC LLC

Saint Paul, MN

$140K - $170K/yr

Other

Medical, Retirement, PTO

Re-posted 7 hours ago

Job description

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. Job SummaryWe are currently seeking a Staff ASIC Design Engineer responsible for developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will collaborate with highly qualified and experienced digital design engineers on the team. You will work closely with verification, analog design, physical design and architecture teams.Key Responsibilities:• Providing leadership to lower-level engineers and working with architects to understand the function and requirements for all types of digital design blocks.• Define, document and design digital/analog interfaces.• Writing detailed implementation plans and specifications for complex design blocks. • Writing Register Transfer Level (RTL) code using industry standard hardware description languages. • Writing lower-level test bench code to verify baseline functionality and features for design blocks.• Writing test plans and coordinating with the Design Verification team to fully verify design blocks.• Synthesizing RTL code using industry standard tools and analyzing results. • Providing RTL updates to meet Power, Performance and Area (PPA) requirements. • Writing and executing plans for the post silicon lab validation. • Providing continued support for design blocks working within a larger system level environment through productization and production. • Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl). • Provide mentorship and guidance to lower-level digital design engineers. Qualifications:• Bachelor’s or master’s degree in electrical or computer engineering. • Relevant prior experience working at this level as a Staff ASIC Design Engineer. • Experience with RTL coding languages and industry common scripting languages. • Technical leadership experience is a plus. What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $140,000.00 - $170,000.00 Annually

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