RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Hillsboro, OR · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
Hillsboro, OR · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
Beaverton, OR · On-site
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write ... Verilog RTL Logic Design experience. Experience writing specifications and converting them to ...
Beaverton, OR · On-site
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:- Write ... Verilog RTL Logic Design experience. Experience writing specifications and converting them to ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Beaverton, OR · On-site
$172K/yr
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use ...
Beaverton, OR · On-site
$172K/yr
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use ...
Beaverton, OR · On-site
$172K/yr
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use ...
Beaverton, OR · On-site
$172K/yr
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$181K - $318K/yr
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
$99.7K - $110.1K
16% of jobs
$110.1K - $120.5K
3% of jobs
$120.5K - $130.9K
4% of jobs
$134K is the 25th percentile. Wages below this are outliers.
$130.9K - $141.3K
6% of jobs
The median wage is $147.9K / yr.
$141.3K - $151.7K
33% of jobs
$151.7K - $162.2K
3% of jobs
$162.2K - $172.6K
2% of jobs
$179.4K is the 75th percentile. Wages above this are outliers.
$172.6K - $183K
12% of jobs
$183K - $193.4K
5% of jobs
$193.4K - $203.8K
4% of jobs
$203.8K - $214.2K
12% of jobs
$99.7K
$159.3K
$214.2K
| Aspect | Entry Level Asic Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL) | Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required |
| Work Environment | Semiconductor companies, chip design teams, hardware development labs | Electronics companies, integrated circuit design teams, hardware development labs |
| Industry Usage | Primarily in ASIC/FPGA chip design | In digital hardware design across various sectors including consumer electronics and telecom |
While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976