... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
MTS Logic Design
Hillsboro, OR · On-site
$86.30 - $160.30/hr
Bachelor's degree in engineering * Knowledge of Verilog/System Verilog * Experience with RTL design and verification * Good communication skills Benefits Rambus offers a competitive compensation ...
MTS Logic Design
Hillsboro, OR · On-site
$86.30 - $160.30/hr
Bachelor's degree in engineering * Knowledge of Verilog/System Verilog * Experience with RTL design and verification * Good communication skills Benefits Rambus offers a competitive compensation ...
Structural Design Engineer
Hillsboro, OR · On-site
Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...
Structural Design Engineer
Hillsboro, OR · On-site
Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...
Job Title: Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...
Job Title: Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
Python programming background Preferred Qualifications ... Experience developing, maintaining, and enhancing an existing system for regressing RTL
New
CAD Engineer - Design Verification Methodology
Beaverton, OR · On-site
$90 - $120/hr
Python programming background Preferred Qualifications ... Experience developing, maintaining, and enhancing an existing system for regressing RTL
New
CPU Microcode Design Engineer
Hillsboro, OR · On-site
$105K - $200K/yr
If you are inspired by solving complex engineering challenges and want your work to directly shape ... RTL logic design using Verilog and debug using industry standard tools * Linux shell, Perl, or ...
CPU Microcode Design Engineer
Hillsboro, OR · On-site
$105K - $200K/yr
If you are inspired by solving complex engineering challenges and want your work to directly shape ... RTL logic design using Verilog and debug using industry standard tools * Linux shell, Perl, or ...
Hardware Design Engineer
Beaverton, OR · On-site
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
Hardware Design Engineer
Beaverton, OR · On-site
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
Hardware Design Engineer
Beaverton, OR · On-site
$64 - $119/hr
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
Hardware Design Engineer
Beaverton, OR · On-site
$64 - $119/hr
Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU Design Timing Engineer
$184K - $324K/yr
... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... RTL to GDS physical design flow Scripting skills to debug flow related issues and make enhancements ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... RTL to GDS physical design flow Scripting skills to debug flow related issues and make enhancements ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... RTL to GDS physical design flow Scripting skills to debug flow related issues and make enhancements ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ... RTL to GDS physical design flow Scripting skills to debug flow related issues and make enhancements ...
Hardware Design Engineer Tektronix Beaverton, OR, United States
Beaverton, OR · On-site
$64 - $119/hr
## Hardware Design EngineerBeaverton, OR, United StatesFind out how well you match with this jobJob ID10183Position SummaryWe are seeking an entry-level Hardware Design Engineer to contribute to the ...
Hardware Design Engineer Tektronix Beaverton, OR, United States
Beaverton, OR · On-site
$64 - $119/hr
## Hardware Design EngineerBeaverton, OR, United StatesFind out how well you match with this jobJob ID10183Position SummaryWe are seeking an entry-level Hardware Design Engineer to contribute to the ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ...
Entry Level Asic Rtl Design Engineer information
See Portland, OR salary details
$99.7K - $110.1K
16% of jobs
$110.1K - $120.5K
3% of jobs
$120.5K - $130.9K
4% of jobs
$134K is the 25th percentile. Wages below this are outliers.
$130.9K - $141.3K
6% of jobs
The median wage is $147.9K / yr.
$141.3K - $151.7K
33% of jobs
$151.7K - $162.2K
3% of jobs
$162.2K - $172.6K
2% of jobs
$179.4K is the 75th percentile. Wages above this are outliers.
$172.6K - $183K
12% of jobs
$183K - $193.4K
5% of jobs
$193.4K - $203.8K
4% of jobs
$203.8K - $214.2K
12% of jobs
$99.7K
$159.3K
$214.2K
How much do entry level asic rtl design engineer jobs pay per year?
As of Aug 19, 2026, the average yearly pay for entry level asic rtl design engineer in Portland, OR is $159,283.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,500.00 and $190,900.00 per year, depending on experience, location, and employer.
What does an entry level ASIC RTL design engineer do?
An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.
What are the key skills and qualifications needed to thrive as an entry level ASIC RTL design engineer?
To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.
What are some typical challenges faced by entry level ASIC RTL design engineers in their first year, and how can they overcome them?
Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.
What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Entry Level Asic Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL) | Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required |
| Work Environment | Semiconductor companies, chip design teams, hardware development labs | Electronics companies, integrated circuit design teams, hardware development labs |
| Industry Usage | Primarily in ASIC/FPGA chip design | In digital hardware design across various sectors including consumer electronics and telecom |
While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Portland, OR?
The most popular types of Asic Rtl Design Engineer jobs in Portland, OR are:
What are popular job titles related to Entry Level Asic Rtl Design Engineer jobs in Portland, OR?
For Entry Level Asic Rtl Design Engineer jobs in Portland, OR, the most frequently searched job titles are:
- Mechanical Engineer No Experience
- Remote Mechanical Design Engineer
- Entry Level Mechanical Design Engineer
- Entry Level Rfic Design Engineer
- Entry Level Serdes Design Engineer
- Entry Level Defense Mechanical Engineer
- Associate Mechanical Design Engineer
- Circuit Design Engineer Assistant
- Junior Mechanical Design Engineer
- Entry Level Design Verification Engineer
What job categories do people searching Entry Level Asic Rtl Design Engineer jobs in Portland, OR look for?
The top searched job categories for Entry Level Asic Rtl Design Engineer jobs in Portland, OR are:
- Mechanical Engineer Firearms Design
- Cpu Rtl Design Engineer
- Mechanical Design Engineering
- Ai Chip Design Rtl
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$184K - $324K/yr
Full-time
Medical, Dental, Retirement
Re-posted 23 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!
Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer, floating-point, and/or load/store execution for our performant cores.
Description
As a CPU Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Preferred Qualifications
Expertise in one or more of the following areas: out-of-order execution, instruction scheduling, integer and floating point execution, load/store execution, cache and memory subsystems
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple’s Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to drive architecture and RTL development of CPU integer, floating-point, and/or load/store execution for our performant cores.
Description
As a CPU Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Preferred Qualifications
Expertise in one or more of the following areas: out-of-order execution, instruction scheduling, integer and floating point execution, load/store execution, cache and memory subsystems
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976