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Entry Level Asic Rtl Design Engineer Jobs in Portland, OR

Rambus.com

MTS Logic Design

Hillsboro, OR · On-site

$100 - $125/hr

Bachelor's degree in engineering * Knowledge of Verilog/System Verilog * Experience with RTL design and verification * Good communication skills Benefits Rambus offers a competitive compensation ...

Noralogic Inc

Structural Design Engineer

Hillsboro, OR · On-site

Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is expected to work ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...

Noralogic Inc

Structural Design Engineer

Hillsboro, OR · On-site

Job Title: Structural Design Job Location: Hillsboro, OR Job Type: Fulltime The resource is ... RTL to netlist) and APR flows from floorplan to converged layout. This will also include, but not ...

Apple

CPU Design Timing Engineer

Beaverton, OR

$184K - $324K/yr

... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...

Apple

CPU Design Timing Engineer

Beaverton, OR

$184K - $324K/yr

... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...

Ralliant

Hardware Design Engineer

Beaverton, OR · On-site

Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...

Apple

CPU Design Timing Engineer

Beaverton, OR

$184K - $324K/yr

... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...

Apple

CPU Design Timing Engineer

Beaverton, OR

$184K - $324K/yr

... RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and ... Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ...

Ralliant

Hardware Design Engineer

Beaverton, OR · On-site

$80 - $100/hr

Position Summary We are seeking an entry-level Hardware Design Engineer to contribute to the design, development, validation, and support of advanced electronic hardware for test and measurement ...

Apple

CPU CDC/RDC/STA Engineer

Beaverton, OR

$184K - $324K/yr

As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...

Apple

CPU CDC/RDC/STA Engineer

Beaverton, OR

$184K - $324K/yr

As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...

Apple

CPU CDC/RDC/STA Engineer

Beaverton, OR

$184K - $324K/yr

As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...

Apple

CPU CDC/RDC/STA Engineer

Beaverton, OR

$184K - $324K/yr

As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as ... RTL, Verification, CAD, and Physical Design teams Preferred Qualifications Experience in ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... sign-off for RTL freeze and tape-out. Description In this role, you will be responsible for ...

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All JobsAsic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Portland, OR

Entry Level Asic Rtl Design Engineer information

See Portland, OR salary details

$99.7K

$159.3K

$214.2K

How much do entry level asic rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for entry level asic rtl design engineer in Portland, OR is $159,283.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,500.00 and $190,900.00 per year, depending on experience, location, and employer.

What does an entry level ASIC RTL design engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an entry level ASIC RTL design engineer?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What are some typical challenges faced by entry level ASIC RTL design engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are popular job titles related to Entry Level Asic Rtl Design Engineer jobs in Portland, OR?

For Entry Level Asic Rtl Design Engineer jobs in Portland, OR, the most frequently searched job titles are:

What job categories do people searching Entry Level Asic Rtl Design Engineer jobs in Portland, OR look for?

The top searched job categories for Entry Level Asic Rtl Design Engineer jobs in Portland, OR are:

Entry Level Asic Rtl Design Engineer jobs near you
Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Portland, OR as of August 2026, with employment types broken down into 85% Full Time, 11% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $159,283 per year, or $76.6 per hour.

MTS Logic Design

Hillsboro, OR • On-site

Rambus.com
Semiconductor and Electronic Component Manufacturing • 501 - 1,000 employees
Learn more about Rambus.comexternal

$100 - $125/hr

Other

Medical, Dental, Retirement

Re-posted 23 days ago

Job description

Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Logic Design Engineer to join our Memory Controller team in Hillsboro, OR. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

As a Design/Application Engineer, you’ll play a pivotal role in designing and delivering our Memory Controller products. In this full‑time role, you’ll report directly to our Director of Engineering. Our Memory Controller Group is dedicated to building and releasing truly differentiated silicon IP products, and your contributions will be instrumental in designing, delivering, and supporting these products.

Rambus offers a flexible work environment, embracing a hybrid approach for most office‑based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities
  • Prepare and test IP deliveries
  • Integrate 3rd party IP
  • Customer support
  • Debug simulation failures
  • Design and verify new IP functionality
Qualifications
  • Bachelor’s degree in engineering
  • Knowledge of Verilog/System Verilog
  • Experience with RTL design and verification
  • Good communication skills
Benefits

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time‑off program, and gym membership.

The US salary range for this full‑time position is $86,300 to $160,300. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job‑related skills, experience, qualifications, work location and market conditions.

EEO Statement

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work.

Rambus is a proud Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or accommodation due to a disability, please feel free to inform us in your application.

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