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Freelance Asic Rtl Design Engineer Jobs in Beaverton, OR

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

RTL Design Engineer

Beaverton, OR · On-site

$120 - $180/hr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

RTL Design Engineer

Hillsboro, OR · On-site

$91K - $128K/yr

As a RTL Design Engineer, you will play a pivotal role in shaping the core logic design and architecture of Intel's cutting-edge CPUs. You will work on developing register transfer level (RTL) coding ...

RTL Design Engineer

Beaverton, OR · On-site

$141K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

... Engineering At least 1+ years of coursework or experience in each the following areas: o Basic Logic Design o Microprocessors o Computer Architecture o Digital design and RTL coding o Verilog ...

RTL Design Engineer

Hillsboro, OR · On-site

$91 - $129/hr

The Role and Impact As a RTL Design Engineer, you will play a pivotal role in shaping the core logic design and architecture of • • • • • 's cutting-edge CPUs. You will work on developing ...

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Freelance Asic Rtl Design Engineer information

See Beaverton, OR salary details

$15

$49

$137

How much do freelance asic rtl design engineer jobs pay per hour?

As of Sep 3, 2026, the average hourly pay for freelance asic rtl design engineer in Beaverton, OR is $49.64, according to ZipRecruiter salary data. Most workers in this role earn between $25.24 and $64.28 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Beaverton, OR?

The most popular types of Asic Rtl Design Engineer jobs in Beaverton, OR are:

What are popular job titles related to Freelance Asic Rtl Design Engineer jobs in Beaverton, OR?

For Freelance Asic Rtl Design Engineer jobs in Beaverton, OR, the most frequently searched job titles are:

What job categories do people searching Freelance Asic Rtl Design Engineer jobs in Beaverton, OR look for?

The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Beaverton, OR are:

Senior ASIC Design Engineer

ServerLogic

Beaverton, OR • On-site

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

Sr/ ASIC Design Engineer
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
  1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
  2. Collaborate with other team members to integrate the block with the full chip
  3. Use Verilog to design and System Verilog for block level verification
  4. Assist the Verification team in reviewing and debugging test cases
  5. Run LINT and CDC checks on the RTL code and fix accordingly.
  6. Assist with synthesis and FPGA emulation.

QUALIFICATIONS -
  1. BA/MS degree and 5+ years of relevant work experience.
  2. Demonstrate knowledge of Verilog for chip design and verification.
  3. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug.
  4. Understanding of digital design and verification practices.
  5. Be able to take a specification, write RTL and simulation vectors to verify their RTL.
  6. One prior RTL design is a requirement.
  7. Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.