Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
$116K - $182K/yr
Senior ASIC Design Engineer Description - HP is the world's leading printing company. We are ... This includes RTL coding, verification, silicon validation, and qualification. * Proactively work ...
$116K - $182K/yr
Senior ASIC Design Engineer Description - HP is the world's leading printing company. We are ... This includes RTL coding, verification, silicon validation, and qualification. * Proactively work ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Own micro‑architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Hillsboro, OR · On-site
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Hillsboro, OR · Hybrid
$127K - $236K/yr
As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · On-site
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Beaverton, OR · On-site
$150 - $210/hr
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications * Experience writing specifications ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Hillsboro, OR · Hybrid
$127K - $287K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Beaverton, OR · On-site
$100 - $130/hr
Description As a Front‑End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and ...
Beaverton, OR · On-site
$100 - $130/hr
Description As a Front‑End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
$24.48 is the 25th percentile. Wages below this are outliers.
$15.51 - $26.60
31% of jobs
The median wage is $33.44 / hr.
$26.60 - $37.70
31% of jobs
$37.70 - $48.79
4% of jobs
$58.50 is the 75th percentile. Wages above this are outliers.
$48.79 - $59.89
10% of jobs
$59.89 - $70.99
9% of jobs
$70.99 - $82.08
5% of jobs
$82.08 - $93.18
0% of jobs
$93.18 - $104.27
8% of jobs
$104.27 - $115.37
0% of jobs
$115.37 - $126.46
0% of jobs
$126.46 - $137.56
1% of jobs
$15
$49
$137
The most popular types of Asic Rtl Design Engineer jobs in Beaverton, OR are:
For Freelance Asic Rtl Design Engineer jobs in Beaverton, OR, the most frequently searched job titles are:
The top searched job categories for Freelance Asic Rtl Design Engineer jobs in Beaverton, OR are:
$127K - $236K/yr
Full-time
Medical, Dental, Retirement
Posted 15 days ago
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Definite Plus:
About Rambus
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $127,400 to $236,600
Sourced by ZipRecruiter
Semiconductor and electronic component manufacturing
501 - 1,000 Employees
Sunnyvale, CA, US
1990
