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Ai Chip Design Rtl Jobs in Portland, OR (NOW HIRING)

Nvidia

Senior CPU Design Engineer

Hillsboro, OR · Hybrid

Implement in RTL and coordinate execution with the verification team to ensure that the design is ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...

Nvidia

Senior VLSI CAD Software Engineer

Hillsboro, OR

$133K - $175K/yr

... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...

Apple

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

... performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Intel Corporation

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $232K/yr

In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions ... Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

Intel

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $232K/yr

In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions ... Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an ... RTL coding and verification * Memory Controller + PHY integration and verification * Customer ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to ... RTL coding and verification * Memory Controller + PHY integration and verification * Customer ...

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to ... RTL coding and verification * Memory Controller + PHY integration and verification * Customer ...

Apple Inc.

CPU Performance Engineer

Beaverton, OR · On-site

$180 - $270/hr

In this highly visible role, you will be at the center of a chip design effort working with all ... Description * Architect cutting-edge CPU performance features in collaboration with RTL and ...

New

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Apple

Physical Design Engineer

Beaverton, OR

$184K - $324K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

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All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Portland, OR

Ai Chip Design Rtl information

See Portland, OR salary details

$85.4K

$147.8K

$193.5K

How much do ai chip design rtl jobs pay per year?

As of Aug 7, 2026, the average yearly pay for ai chip design rtl in Portland, OR is $147,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,200.00 and $144,200.00 per year, depending on experience, location, and employer.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Portland, OR as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $147,800 per year, or $71.1 per hour.

Senior Physical Design and Timing Engineer

Nvidia

Hillsboro, OR • Hybrid

Full-time

Re-posted 6 days ago

Nvidia rating

9.6

Company rating: 9.6 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

8th of 242 rated software companies

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.

What you'll be doing:

  • Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.

  • Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

  • Work in a cross-functional environment interacting with multiple teams.

What we need to see:

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 3+ years of experience in physical design, synthesis, and timing.

  • Strong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs.

  • Demonstrated success improving power, performance, and area through design improvements, critical-path planning and crafting,or methodology/workflow improvements.

  • Hands-on experiencein block, sub-chip, and full-chip levelStatic Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.

  • Expertise and in-depth knowledge of industry-standard EDA tools.

  • Proficiency in Python, Tcl, Perl, Make, or similar scripting languages as well as AI/ML/DL/LLMs.

Ways to stand out from the crowd:

  • Physical design experience onhigh-performance CPUs, GPUs, LPUs, or AI accelerator designs.

  • Expertise or innovation in advanced physical design & circuits optimizations, clocking, or timing-closure strategies.

  • Experience in developing scalable optimization and signoff solutions through automation or AI/Agentic framework.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until July 24, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What Nvidia employees say

Pay

Benefits

Hours and flexibility

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Get the full story on Breakroom

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About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

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