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Ai Chip Design Rtl Jobs in Portland, OR (NOW HIRING)

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

New

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

In this highly transparent role, you will be at the center of a chip design effort collaborating ... RTL to Emulation is a huge plus Good understanding of any Standard Emulator (Palladium, Veloce ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

In this highly transparent role, you will be at the center of a chip design effort collaborating ... RTL to Emulation is a huge plus Good understanding of any Standard Emulator (Palladium, Veloce ...

Apple

Emulation Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

In this highly transparent role, you will be at the center of a chip design effort collaborating ... Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a huge plus Good ...

Apple

Emulation Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

In this highly transparent role, you will be at the center of a chip design effort collaborating ... Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a huge plus Good ...

Nvidia

Senior CPU Design Engineer

Hillsboro, OR · Hybrid

Implement in RTL and coordinate execution with the verification team to ensure that the design is ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...

Nvidia

Senior VLSI CAD Software Engineer

Hillsboro, OR · On-site

$133K - $175K/yr

... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...

Apple

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

... performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

Rambus.com

PE Logic Design

Hillsboro, OR · On-site

$127 - $237/hr

Overview Rambus, a premier chip and silicon IP provider,is seekingto hirean exceptional ... Ownmicro-architecturedefinitionand RTL designfor critical blocks such as schedulers, command ...

New

Rambus

PE Logic Design

Hillsboro, OR · On-site

$127K - $236K/yr

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional ... Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ...

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All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Portland, OR

Ai Chip Design Rtl information

See Portland, OR salary details

$85.4K

$147.8K

$193.5K

How much do ai chip design rtl jobs pay per year?

As of Aug 23, 2026, the average yearly pay for ai chip design rtl in Portland, OR is $147,800.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,200.00 and $144,200.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are popular job titles related to Ai Chip Design Rtl jobs in Portland, OR?

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What job categories do people searching Ai Chip Design Rtl jobs in Portland, OR look for?

The top searched job categories for Ai Chip Design Rtl jobs in Portland, OR are:

Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Portland, OR as of August 2026, with employment types broken down into 87% Full Time, 9% Part Time, and 4% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $147,800 per year, or $71.1 per hour.

Principal PCIe CXL RTL Design Engineer

Rambus

Hillsboro, OR • Hybrid

Full-time

Medical, PTO

Re-posted 17 days ago

Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. 

This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe and CXL standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues. 

Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Benefits include an excellent health insurance, Employee Stock Purchase Plan, an extra day of vacation per quarter, regular team lunches and breakfasts and a great team atmosphere.

Responsibilities
  • Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP 
  • Implement these designs in System Verilog 
  • Collaborate with the verification team to verify the IPs 
  • Participate in prototyping of the IPs in cutting edge FPGAs 

 

Qualifications
  • RTL coding: Verilog / System Verilog 
  • Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. 
  • 5+ years of experience with RTL Design 
  • Good English skills, communication skills, and willingness to work with an international team. 

Additional Desirable skills: 

  • Knowledge of PCIe / CXL 

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems.  

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. 

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. 

 Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.  

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. 

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. 

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check outrambus.com/careers/. 

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