ZipRecruiter

Log In

1

Ai Chip Design Rtl Jobs (NOW HIRING)

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156K - $160K/yr

Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline ... Arithmetic circuit design related to general datapath circuits, ML and AI circuits. * Arithmetic ...

Cerebras Systems

Lead RTL Design Engineer

Sunnyvale, CA · On-site

$175K - $275K/yr

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture ... This role requires deep expertise in RTL design and integration, with a strong focus on delivering ...

Architect Labs

$250/hr

We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ... Own the on-chip fabric RTL end-to-end : from NoC topology and router microarchitecture through code ...

Google

RTL Design Engineer, TPU

Sunnyvale, CA · On-site

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

Google

Senior RTL Design Engineer, TPU

Sunnyvale, CA · On-site

Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc ... About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You ...

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

Design realistic chip architecture, RTL, debugging, and verification challenges based on real ... Analyze where AI models struggle with hardware engineering concepts, debugging, verification ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

previous pagenext page

Showing results 21-40

All JobsAi Chip Design Rtl Jobs

Ai Chip Design Rtl information

See salary details

$80.5K

$139.4K

$182.5K

How much do ai chip design rtl jobs pay per year?

As of Sep 9, 2026, the average yearly pay for ai chip design rtl in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

More about Ai Chip Design Rtl jobs

What cities are hiring for Ai Chip Design Rtl jobs?

Cities with the most Ai Chip Design Rtl job openings:

What states have the most Ai Chip Design Rtl jobs?

States with the most job openings for Ai Chip Design Rtl jobs include:

What job categories do people searching Ai Chip Design Rtl jobs look for?

The top searched job categories for Ai Chip Design Rtl jobs are:

What other helpful pages are available for Ai Chip Design Rtl?

Other pages related to Ai Chip Design Rtl:

Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in the United States as of September 2026, with employment types broken down into 75% Full Time, and 25% Contract. Highlights an 87% In-person, and 13% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

SoC Design Engineer

Santa Clara, CA

OMNIVISION
Software Development • 1 - 5K employees
Learn more about OMNIVISIONexternal

$156K - $160K/yr

Full-time

Re-posted 4 days ago

Job description

Job Title: SoC Design Engineer
 
Job Duties:  
 
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP design, analysis, integration, and validation. Collaborate with physical design teams on floor-planning, timing closure, and DFT implementation. Conduct timing control logic design and static timing analysis (STA) for sensor interfaces and mixed-signal integration. Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline according to PRD/design specification and system architecture of SoC products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm and application engineers for project-based microarchitecture improvements. Conduct silicon validation, debugging and tuning.
 
Requirements:
 
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
 
Required skills and/or academic training in the following: 
 
  • Arithmetic circuit design related to general datapath circuits, ML and AI circuits.
  • Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and debug.
  • Design and design debug with System Verilog; Logic design and analysis.  
  • Processing Subsystem, including superscalar out-of-order cores, multicore and heterogeneous processors, and purpose-specific accelerators.  
  • Design tools, such as microarchitecture simulators, RTL synthesis tools, and modeling for area, power, and thermal. 
  • FPGA platforms to compute acceleration.  
  • FPGAs technology, architecture and applications.  
  • Register-Transfer Level (RTL) hardware design.  
  • Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks.  
  • Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal chip design.  
  • Full-chip integration and verification for tapeout.  
 
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
 

Apply