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Ai Chip Design Rtl Jobs in Oxnard, CA (NOW HIRING)

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Ai Chip Design Rtl information

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$85.2K

$147.6K

$193.3K

How much do ai chip design rtl jobs pay per year?

As of Aug 27, 2026, the average yearly pay for ai chip design rtl in Oxnard, CA is $147,587.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What job categories do people searching Ai Chip Design Rtl jobs in Oxnard, CA look for?

The top searched job categories for Ai Chip Design Rtl jobs in Oxnard, CA are:

What cities near Oxnard, CA are hiring for Ai Chip Design Rtl jobs?

Cities near Oxnard, CA with the most Ai Chip Design Rtl job openings:

Ai Chip Design Rtl jobs near you

Staff Analog Mixed-Signal Design - Optical

Marvell Technology, Inc.

Westlake Village, CA • On-site

Full-time

Life, Retirement

Re-posted 26 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's Broadband Analog group designs physical layer ICs for high-speed optical fiber data communication, such as Transimpedance Amplifiers (TIAs), and drivers for Silicon Photonic (SiPho), Electro-absorption Modulators (EAMs), and Mach-Zehnder Interferometer Modulators (MZMs). This group is the market leader in delivering TIAs and Drivers for Data Center and Telecom markets. We address the bandwidth, capacity and power issues faced by cloud computing and mega data center networks. Our world class group leverages our core competencies in advanced circuit design to solve the world's ever-increasing desire to transmit more data for less power with fewer errors. We are continually first to market in Data Center, Metro and Long-Haul applications. As a member of the design group, the candidate will be responsible for design and validation of FET and BiCMOS circuits for high-speed broadband ICs that serve these applications.
What You Can Expect
Marvell is seeking an RF and Analog Design Engineer to contribute to the development of multi-tens of GHz transimpedance amplifiers (TIAs). These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs best in class for coherent long-haul and metro systems as well as PAM4 data center systems. In this role you will be responsible for:
  • Active-circuit design.
  • Design of leading edge transimpedance amplifiers, using both SiGe BiCMOS and the most advanced CMOS FinFET technologies, where circuit performance will need to transcend beyond industry leading products.
  • Development of transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
  • Design of high-performance broadband analog circuits for optical front-end receivers.
  • Design of various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc.
  • Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support.

What We're Looking For
  • Bachelor's degree in Electrical Engineering with 3-5 years of industry experience OR Master's or PhD degree in Electrical Engineering with 1+ years of industry experience in the area of designing high-performance RF/Analog Receiver/TIA.
  • Proven experience in high-performance receiver design including both chip tape-out AND lab evaluation.
  • Solid experience in.
    • Using EDA CAD tools
    • Performing Analog Custom Layout
  • Experience in measuring IC performance and debug of design to correlate simulations to measurements.
  • Deep understanding of fundamentals, including:
    • Detailed transistor level design.
    • Device physics.
    • Control/Feedback loop stability analysis.
  • Direct project experience in at least one of the following areas is a plus:
    • Automatic gain-control loops.
    • High precision analog circuits including linear regulators, current sensors, bandgaps and DAC/ADC.
    • Continuous-time linear equalizers.
  • Experience in Package-System integration issues is desired.
  • Project experience in using different technologies. (SiGe BiCMOS and FinFET CMOS are pluses)
  • A team-player.
  • Experience in the following is a plus:
    • Overseeing and mentoring junior circuit designers.
    • Experience as chip lead with success in silicon.
    • Experience in taking chips to mass production.
    • Ability to translate chip level specifications into architecture.
  • Strong communication, presentation and documentation skills.

Expected Base Pay Range (USD)
126,700 - 187,480, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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