ZipRecruiter

Log In

1

Sram Memory Design Jobs in California (NOW HIRING)

7Rays Semiconductors

CA · On-site

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test ... design, routing channels, and macro assembly. · Carry out, debug, and complete DRC, LVS, ERC ...

Qualcomm

Memory Designer

San Diego, CA · On-site

$115K - $173K/yr

As part of the Memory IP team, you will take innovative and revolutionary ideas and turn them into ... Strong knowledge in CPU L1/L2 cache design, compiler SRAM/Register File architectures and advanced ...

next page

Showing results 1-20

All JobsSram Memory Design JobsSram Memory Design Jobs in California

Sram Memory Design information

See California salary details

$9

$19

$36

How much do sram memory design jobs pay per hour?

As of Jul 28, 2026, the average hourly pay for sram memory design in California is $19.12, according to ZipRecruiter salary data. Most workers in this role earn between $14.23 and $21.35 per hour, depending on experience, location, and employer.

What is the difference between Sram Memory Design vs DRAM Memory Design?

AspectSram Memory DesignDRAM Memory Design
FocusDesigning static RAM cells, optimizing speed and powerDesigning dynamic RAM cells, focusing on density and refresh management
Work EnvironmentSemiconductor companies, hardware design labsMemory chip manufacturers, integrated circuit design teams
CredentialsElectrical engineering, specialized in digital and memory designElectrical engineering, with emphasis on memory architectures

Sram Memory Design and DRAM Memory Design both involve memory chip development but differ in cell technology and application focus. Sram is faster and used for cache memory, while DRAM offers higher density for main memory. Understanding these differences helps in choosing the right design approach for specific hardware needs.

What is SRAM memory design?

SRAM memory design refers to the process of creating Static Random Access Memory (SRAM) circuits used in electronic devices for fast, temporary data storage. Designers focus on optimizing speed, power consumption, and area while ensuring data stability and reliability. The process involves schematic design, layout, verification, and testing of SRAM cells and arrays to meet specific performance requirements. SRAM is commonly used in cache memory and other high-speed applications because it retains data as long as power is supplied, without needing to be refreshed like DRAM.

What are some common challenges faced by engineers in SRAM Memory Design and how can they be addressed?

Engineers in SRAM Memory Design often encounter challenges such as optimizing for low power consumption while maintaining high performance and ensuring data integrity under various process, voltage, and temperature variations. Addressing these challenges requires close collaboration with process technology teams, rigorous simulation and verification, and frequent design reviews. Additionally, balancing area efficiency with speed can be complex, so ongoing learning and teamwork are essential for success in this role.

What are the key skills and qualifications needed to thrive as an SRAM Memory Design Engineer, and why are they important?

To thrive as an SRAM Memory Design Engineer, you need a strong background in electrical engineering, semiconductor physics, and circuit design, often supported by a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, along with knowledge of industry standards, is typically required. Analytical thinking, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies are essential for designing reliable, high-performance memory circuits that meet stringent requirements for speed, power, and manufacturability.
What are popular job titles related to Sram Memory Design jobs in California? For Sram Memory Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Sram Memory Design jobs in California look for? The top searched job categories for Sram Memory Design jobs in California are:
What cities in California are hiring for Sram Memory Design jobs? Cities in California with the most Sram Memory Design job openings:
Sram Memory Design jobs near you
Infographic showing various Sram Memory Design job openings in California as of July 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $39,777 per year, or $19.1 per hour.
Sr. SRAM Layout Design Engineer

Sr. SRAM Layout Design Engineer

USG, Inc.

Santa Clarita, CA • On-site

Other

Posted 6 days ago

USG rating

8.4

Company rating: 8.4 out of 10

Based on 57 frontline employees who took The Breakroom Quiz

50th of 535 rated manufacturers

Job description

Job Title: Sr. SRAM Layout Design Engineer

Location: Santa Clara, CA

Interview: Video Interview

Description:

SRAM 

Mixed signal Analog not needed

Min 10years experience 

What you will be doing:

· Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.

· Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.

· Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.

· Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.

· Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.

· Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.

· Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.

· Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.

· Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

What we need to see:

· Have a BSEE or equivalent experience

· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

· Solid grasp of SRAM and memory layout principles.

· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

· Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.

· Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.

· Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

· Knowledge of layout automation or AI tools is a definite plus.

eye

What USG employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply