Overview of Role We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior ...
New
Overview of Role We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior ...
New
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... routing channels, and macro assembly. · Carry out, debug, and complete DRC, LVS, ERC, antenna, and ...
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... routing channels, and macro assembly. · Carry out, debug, and complete DRC, LVS, ERC, antenna, and ...
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... routing channels, and macro assembly. · Carry out, debug, and complete DRC, LVS, ERC, antenna, and ...
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... routing channels, and macro assembly. · Carry out, debug, and complete DRC, LVS, ERC, antenna, and ...
Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). * Optimize SRAM designs for ...
Quick apply
Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). * Optimize SRAM designs for ...
Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). * Optimize SRAM designs for ...
Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). * Optimize SRAM designs for ...
Experience in memory circuit design in one of ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Experience in memory circuit design in one of ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Experience in memory circuit design in one of ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Experience in memory circuit design in one of ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with ... Analyze projected SRAM yield per device versus redundancy requirements * Run experiments using ...
Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with ... Analyze projected SRAM yield per device versus redundancy requirements * Run experiments using ...
Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with ... Analyze projected SRAM yield per device versus redundancy requirements * Run experiments using ...
Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with ... Analyze projected SRAM yield per device versus redundancy requirements * Run experiments using ...
Memory Designer
San Diego, CA · On-site
$115K - $173K/yr
As part of the Memory IP team, you will take innovative and revolutionary ideas and turn them into ... Strong knowledge in CPU L1/L2 cache design, compiler SRAM/Register File architectures and advanced ...
Memory Designer
San Diego, CA · On-site
$115K - $173K/yr
As part of the Memory IP team, you will take innovative and revolutionary ideas and turn them into ... Strong knowledge in CPU L1/L2 cache design, compiler SRAM/Register File architectures and advanced ...
Experience in memory circuit design (SRAM/DRAM/FLASH/ROM/OPT, etc) * Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) * Ability to develop Verilog/Verilog-A ...
Experience in memory circuit design (SRAM/DRAM/FLASH/ROM/OPT, etc) * Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python) * Ability to develop Verilog/Verilog-A ...
Design custom memory circuits and architectures tailored specifically for AI and HPC applications. * Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align ...
Design custom memory circuits and architectures tailored specifically for AI and HPC applications. * Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align ...
Design custom memory circuits and architectures tailored specifically for AI and HPC applications. * Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align ...
Design custom memory circuits and architectures tailored specifically for AI and HPC applications. * Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align ...
Staff Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
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Staff Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Senior Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Quick apply
Senior Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Senior Engineer, RTL Design
San Jose, CA · On-site
Senior Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Senior Engineer, RTL Design
San Jose, CA · On-site
Senior Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Staff Engineer, RTL Design
San Jose, CA · On-site
Staff Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Staff Engineer, RTL Design
San Jose, CA · On-site
Staff Engineer, RTL Design Overview The Memory Solutions Lab (MSL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
... Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in ... What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL ...
... Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in ... What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL ...
Memory Designer
San Diego, CA · On-site
$164K - $246K/yr
As part of the Memory IP team, you will take innovative and revolutionary ideas and turn them into ... Knowledge in CPU L1/L2 cache design, compiler SRAM/Register File architectures and advanced custom ...
Memory Designer
San Diego, CA · On-site
$164K - $246K/yr
As part of the Memory IP team, you will take innovative and revolutionary ideas and turn them into ... Knowledge in CPU L1/L2 cache design, compiler SRAM/Register File architectures and advanced custom ...
Sram Memory Design information
See California salary details
$9.01 - $11.50
9% of jobs
$11.50 - $13.98
8% of jobs
$14.62 is the 25th percentile. Wages below this are outliers.
$13.98 - $16.46
28% of jobs
The median wage is $17.12 / hr.
$16.46 - $18.94
16% of jobs
$20.63 is the 75th percentile. Wages above this are outliers.
$18.94 - $21.42
20% of jobs
$21.42 - $23.90
9% of jobs
$23.90 - $26.38
4% of jobs
$26.38 - $28.86
1% of jobs
$28.86 - $31.34
1% of jobs
$31.34 - $33.82
1% of jobs
$33.82 - $36.30
2% of jobs
$9
$19
$36
How much do sram memory design jobs pay per hour?
As of Jul 29, 2026, the average hourly pay for sram memory design in California is $19.12, according to ZipRecruiter salary data. Most workers in this role earn between $14.23 and $21.35 per hour, depending on experience, location, and employer.
What is the difference between Sram Memory Design vs DRAM Memory Design?
| Aspect | Sram Memory Design | DRAM Memory Design |
|---|---|---|
| Focus | Designing static RAM cells, optimizing speed and power | Designing dynamic RAM cells, focusing on density and refresh management |
| Work Environment | Semiconductor companies, hardware design labs | Memory chip manufacturers, integrated circuit design teams |
| Credentials | Electrical engineering, specialized in digital and memory design | Electrical engineering, with emphasis on memory architectures |
Sram Memory Design and DRAM Memory Design both involve memory chip development but differ in cell technology and application focus. Sram is faster and used for cache memory, while DRAM offers higher density for main memory. Understanding these differences helps in choosing the right design approach for specific hardware needs.
What is SRAM memory design?
SRAM memory design refers to the process of creating Static Random Access Memory (SRAM) circuits used in electronic devices for fast, temporary data storage. Designers focus on optimizing speed, power consumption, and area while ensuring data stability and reliability. The process involves schematic design, layout, verification, and testing of SRAM cells and arrays to meet specific performance requirements. SRAM is commonly used in cache memory and other high-speed applications because it retains data as long as power is supplied, without needing to be refreshed like DRAM.
What are some common challenges faced by engineers in SRAM Memory Design and how can they be addressed?
Engineers in SRAM Memory Design often encounter challenges such as optimizing for low power consumption while maintaining high performance and ensuring data integrity under various process, voltage, and temperature variations. Addressing these challenges requires close collaboration with process technology teams, rigorous simulation and verification, and frequent design reviews. Additionally, balancing area efficiency with speed can be complex, so ongoing learning and teamwork are essential for success in this role.
What are the key skills and qualifications needed to thrive as an SRAM Memory Design Engineer, and why are they important?
To thrive as an SRAM Memory Design Engineer, you need a strong background in electrical engineering, semiconductor physics, and circuit design, often supported by a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, along with knowledge of industry standards, is typically required. Analytical thinking, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies are essential for designing reliable, high-performance memory circuits that meet stringent requirements for speed, power, and manufacturability.
What are popular job titles related to Sram Memory Design jobs in California? For Sram Memory Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Sram Memory Design jobs in California look for? The top searched job categories for Sram Memory Design jobs in California are:
What cities in California are hiring for Sram Memory Design jobs? Cities in California with the most Sram Memory Design job openings:
Future Opportunity: Senior Memory Design Engineer (SRAM/Compiler Focus)(7367)
San Jose, CA • Hybrid
Other
Posted 2 days ago
New
TSMC rating
8.0
Based on 21 frontline employees who took The Breakroom Quiz
54th of 156 rated electronics manufacturers
Job description
This position is not currently open; however, we are posting for future positions that range from Junior to Senior levels for our San Jose Design Center.
Overview of Role
We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior Memory Design Engineer, you will leverage TSMC's leading-edge process technologies and comprehensive design enablement solutions to drive groundbreaking innovations for the global semiconductor industry. Join us in the San Jose Design Office and be part of the team that pushes the boundaries of what's possible in advanced memory design.
You will report to the Director of Memory Design Team in San Jose, California. We operate on a hybrid work schedule with 4 days in the office, fostering a collaborative and dynamic environment.
Responsibilities
- Drive the design, characterization, and verification methodology for advanced Memory IP at the compiler level, directly impacting SoC designs in customer products.
- Implement custom digital and analog circuits for advanced SRAM/DRAM/Non-Volatile memory designs, collaborating closely with logic and architecture teams to define comprehensive specifications.
- Lead and execute memory compiler development, including timing/power characterization, netlist/layout tiling, and IR/EM flow analysis.
- Oversee and provide technical guidance for layout optimization, compiler coding, and the interpretation of silicon testing results and debug activities.
- Conduct silicon debug and chip failure analysis for various customers, contributing to continuous improvement and next-generation design.
- Perform PPPA (Power, Performance, Area) optimization to meet stringent customer requirements across various technology nodes.
- Develop and implement design schemes for low power (LS/DS/SD), dual-rail, BIST, and foundry-based Write-Assist and Read-Assist circuitry.
- Collaborate strategically with cross-functional teams and Headquarters in Hsinchu, Taiwan, ensuring functional products are delivered efficiently.
- Act as a hands-on technical contributor for all compiler-related work, encompassing circuit design, automation, and verification.
Minimum Requirements
- Master's degree in Electrical/Computer Engineering with 5+ years of related work experience; or a Bachelor's degree in Electrical/Computer Engineering with 7+ years of related work experience.
- Demonstrated expertise in Memory IP design, characterization, and verification methodologies at the compiler level.
- In-depth knowledge and hands-on experience with advanced SRAM compiler development, utilizing Cadence and Synopsys circuit design environments.
- Proven experience in advanced technology node circuit design (TSMC N10 or below, including TS7, GF22, Intel10, etc.) and layout.
- Expertise in scripting languages such as Perl/Shell/TCL/Python for design automation, simulation, and QA flow.
- Strong understanding of bitcell analysis, critical margin validation, and simulation setup.
- Experience in designing low-power techniques (LS/DS/SD), dual-rail, BIST, and foundry-based Write-Assist/Read-Assist circuitry.
Preferred Requirements
- Ph.D. in Electrical/Computer Engineering with a focus on memory circuit design.
- Exposure to TSMC N5 and below technology.
- Experience leading or coordinating design projects, including collaboration with layout and QA engineers.
- Advanced static timing analysis and sign-off capabilities.
- Track record in multi-million gate design production tapeouts.
- Strong interpersonal skills, excellent teamwork attitude, and the ability to work effectively under pressure in a fast-paced, collaborative environment.
- Knowledge of layout optimization techniques to improve yield, reduce RC loading, and optimize design size.
- Published research or patents related to memory circuit design.
Company Description
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
- The world's leading dedicated semiconductor foundry
- The technology leader with a strong reputation for manufacturing excellence
- Advancing semiconductor manufacturing innovations to enable the future of technology
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world's leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry's leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
TSMC Technology Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.