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Sram Memory Design Jobs in California (NOW HIRING)

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA · On-site

$150K - $250K/yr

Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA · On-site

$150K - $250K/yr

Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA

$150K - $250K/yr

Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA · On-site

$150K - $250K/yr

Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

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How much do sram memory design jobs pay per hour?

As of Aug 20, 2026, the average hourly pay for sram memory design in California is $19.12, according to ZipRecruiter salary data. Most workers in this role earn between $14.23 and $21.35 per hour, depending on experience, location, and employer.

What is SRAM memory design?

SRAM memory design refers to the process of creating Static Random Access Memory (SRAM) circuits used in electronic devices for fast, temporary data storage. Designers focus on optimizing speed, power consumption, and area while ensuring data stability and reliability. The process involves schematic design, layout, verification, and testing of SRAM cells and arrays to meet specific performance requirements. SRAM is commonly used in cache memory and other high-speed applications because it retains data as long as power is supplied, without needing to be refreshed like DRAM.

What are the key skills and qualifications needed to thrive as an SRAM memory design engineer?

To thrive as an SRAM Memory Design Engineer, you need a strong background in electrical engineering, semiconductor physics, and circuit design, often supported by a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, along with knowledge of industry standards, is typically required. Analytical thinking, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies are essential for designing reliable, high-performance memory circuits that meet stringent requirements for speed, power, and manufacturability.

What are some common challenges faced by engineers in SRAM memory design and how can they be addressed?

Engineers in SRAM Memory Design often encounter challenges such as optimizing for low power consumption while maintaining high performance and ensuring data integrity under various process, voltage, and temperature variations. Addressing these challenges requires close collaboration with process technology teams, rigorous simulation and verification, and frequent design reviews. Additionally, balancing area efficiency with speed can be complex, so ongoing learning and teamwork are essential for success in this role.

What is the difference between Sram Memory Design vs DRAM Memory Design?

AspectSram Memory DesignDRAM Memory Design
FocusDesigning static RAM cells, optimizing speed and powerDesigning dynamic RAM cells, focusing on density and refresh management
Work EnvironmentSemiconductor companies, hardware design labsMemory chip manufacturers, integrated circuit design teams
CredentialsElectrical engineering, specialized in digital and memory designElectrical engineering, with emphasis on memory architectures

Sram Memory Design and DRAM Memory Design both involve memory chip development but differ in cell technology and application focus. Sram is faster and used for cache memory, while DRAM offers higher density for main memory. Understanding these differences helps in choosing the right design approach for specific hardware needs.

What are popular job titles related to Sram Memory Design jobs in California?

For Sram Memory Design jobs in California, the most frequently searched job titles are:

What job categories do people searching Sram Memory Design jobs in California look for?

The top searched job categories for Sram Memory Design jobs in California are:

What cities in California are hiring for Sram Memory Design jobs?

Cities in California with the most Sram Memory Design job openings:

Sram Memory Design jobs near you
Infographic showing various Sram Memory Design job openings in California as of August 2026, with employment types broken down into 91% Full Time, 6% Part Time, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution, with an average salary of $39,777 per year, or $19.1 per hour.

FPGA Design Engineer - Avionics

E-Space

Saratoga, CA • On-site

$150K - $250K/yr

Full-time

Medical, PTO

Re-posted 21 days ago

Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We're intentional, we're unapologetically curious and we're 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are looking for FPGA Design Engineers to develop, implement, and verify FPGA firmware for satellite avionics systems. You will work across multiple boards and subsystems, designing RTL for flight computers, payload processing, communications, and sensor interfaces. The role requires strong digital design fundamentals and the ability to deliver reliable, radiation-tolerant FPGA designs for a space environment.

Key Responsibilities:
  • Design and implement RTL in SystemVerilog or VHDL for satellite avionics FPGAs across a variety of FPGA platforms.
  • Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication.
  • Perform FPGA resource and size estimation including logic, memory, and DSP budgeting.
  • Implement clock-domain-crossing (CDC) design techniques and verify timing closure across designs.
  • Design clock/reset tree architectures and manage timing-closure strategies for complex multi-clock designs.
  • Develop SPI, IC, GPIO, and other low-speed peripheral interfaces alongside high-speed transceiver links.
  • Apply fault-tolerant digital design techniques including TMR, ECC, scrubbing, and SEE mitigation.
  • Perform synthesis and place-and-route using vendor toolchains, including custom placement constraints.
  • Support board bring-up by developing configuration, interface verification, and debug test sequences.
  • Collaborate with digital design, power, and PCB layout engineers to ensure FPGA support circuitry meets requirements.
Required Qualifications:
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of FPGA design experience in aerospace, defense, or high-reliability systems.
  • Proficiency in SystemVerilog and/or VHDL for RTL design.
  • Experience with FPGA synthesis, place-and-route, and timing closure workflows.
  • Demonstrated knowledge of AXI or similar bus protocols and interface design.
  • Experience with clock-domain crossing techniques, FIFO design, and multi-clock architectures.
  • Understanding of radiation effects on FPGAs and mitigation strategies (TMR, ECC, scrubbing).
Preferred Qualifications:
  • Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based, anti-fuse architectures).
  • Background in signal processing (FFT, FIR/IIR filters) and DSP integration.
  • Experience with transceiver design and high-speed serial communications on FPGAs.
  • Exposure to DAC/ADC interfaces and mixed-signal digital handling.
  • Experience with satellite or spacecraft FPGA applications.
  • Proficiency in Python or TCL scripting for automation and build infrastructure.
Tools & Technologies:
  • FPGA vendor toolchains (synthesis, place-and-route, timing analysis)
  • RTL simulation tools (e.g., VCS, QuestaSim, or equivalent)
  • Python, TCL, or shell scripting for build automation
  • Makefiles for FPGA build workflows
Additional Requirements
This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.
$150,000 - $250,000 a year

Why E-Space is right for you:

As a member of our team, you will play a crucial role in driving our success.  Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals.  In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry.  

We want you to make the most of your journey at E-Space. That's why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space:

An opportunity to really make a difference
Sustainability at our core
Fair and honest workplace
Innovative thinking is encouraged
Competitive salaries
Continuous learning and development
Health and wellness care options
Financial solutions for the future
Optional legal services (US only)
Paid holidays
Paid time off

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
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