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Ic Layout Manager Jobs in California (NOW HIRING)

MediaTek Research Lab Inc.

IC Layout engineer

Irvine, CA · On-site

$85.90 - $137.50/hr

Work closely with the design team to develop high‑quality layouts for product, data‑converters, power management circuitry, and various other IP. * Perform layout in CMOS or FinFET technologies ...

Qorvo, Inc.

Staff Layout Design Engineer

Sacramento, CA

$144K - $187K/yr

... Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentor's Calibre tools ... Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC ...

Cisco

IC Package Layout Team Leader

San Jose, CA · On-site

$210K - $305K/yr

Partner with the global Package Layout Manager and other regional leaders to align methodologies, tools, best practices, and engineering standards across sites. Contribute to hiring, onboarding ...

Cisco

IC Package Layout Team Leader

San Jose, CA · On-site

$210K - $305K/yr

... Manager and other regional leaders to align methodologies, tools, best practices, and engineering standards across sites. • Contribute to hiring, onboarding, mentoring, and development of layout ...

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Infographic showing various Ic Layout Manager job openings in California as of August 2026, with employment types broken down into 82% Full Time, 15% Part Time, and 3% Contract. Highlights an 79% Physical, 3% Hybrid, and 18% Remote job distribution.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA

Full-time

Re-posted 4 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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