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Remote Pdk Engineer information

What is a Remote PDK Engineer?

A Remote PDK (Process Design Kit) Engineer is a professional who develops, maintains, and supports process design kits for semiconductor manufacturing, while working remotely. PDKs are essential toolkits that enable electronic design automation (EDA) tools to accurately model and simulate integrated circuit fabrication processes. These engineers collaborate with foundries, EDA tool vendors, and design teams to ensure that the PDKs are up-to-date, functional, and compatible with various design flows. Working remotely allows them to contribute from anywhere, often requiring strong communication and self-management skills. Their work is vital for ensuring efficient and accurate chip design and manufacturing.

What are the key skills and qualifications needed to thrive as a Remote PDK Engineer?

To thrive as a Remote PDK Engineer, you need a solid background in electrical engineering, semiconductor device physics, and experience with Process Design Kit (PDK) development, usually backed by a relevant degree. Proficiency in EDA tools like Cadence Virtuoso, Mentor Graphics, and scripting languages such as Python or TCL, as well as familiarity with industry-standard process nodes, is essential. Strong problem-solving skills, attention to detail, and clear communication are vital for collaborating with global teams and addressing technical challenges remotely. These competencies ensure accurate PDK development, effective teamwork, and successful integration of design flows in the semiconductor industry.

What are some typical challenges faced by Remote PDK Engineers when collaborating with global teams?

Remote PDK Engineers often work with colleagues across different time zones and cultures, which can make communication and coordination challenging. It's common to rely heavily on digital collaboration tools and detailed documentation to ensure clarity and continuity in project tasks. Proactive communication, flexibility in meeting times, and a strong self-management skill set are essential for overcoming these hurdles. Establishing clear workflows and regular check-ins also help maintain alignment and productivity within the dispersed team.

What is the difference between Remote Pdk Engineer vs Remote ASIC Design Engineer?

AspectRemote Pdk EngineerRemote ASIC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, familiarity with PDKsBachelor's/Master's in Electrical Engineering or Computer Engineering, experience with ASIC design tools
Work EnvironmentDesign labs, remote collaboration, EDA toolsDesign teams, remote or onsite, EDA and simulation tools
Industry UsageSemiconductor foundries, chip design companiesIntegrated circuit design firms, semiconductor companies

While both roles involve semiconductor design, a Remote Pdk Engineer focuses on developing and validating process design kits, whereas a Remote ASIC Design Engineer works on designing integrated circuits. Both require strong technical skills and industry knowledge, but their daily tasks and focus areas differ.

What are the most commonly searched types of Pdk Engineer jobs in California?

The most popular types of Pdk Engineer jobs in California are:

What are popular job titles related to Remote Pdk Engineer jobs in California?

For Remote Pdk Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Remote Pdk Engineer jobs in California look for?

The top searched job categories for Remote Pdk Engineer jobs in California are:

What cities in California are hiring for Remote Pdk Engineer jobs?

Cities in California with the most Remote Pdk Engineer job openings:

Remote Pdk Engineer jobs near you
Infographic showing various Remote Pdk Engineer job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% Remote job distribution.

High-Speed Analog Layout Design Engineer

Celero Communications, Inc.

Irvine, CA • On-site, Remote

$217K/yr

Full-time

Posted 19 days ago

Job description

Senior to Principal High-Speed Analog Layout Design Engineer roles
Locations: Irvine, CA or San Jose, CA or remote
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
 
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
 
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
 
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
 
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
 
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
 
Note: Since we have several roles available, candidate job level will be evaluated during interview process.